Hardware Implementation of Min-Sum Decoder for Quasi-Cyclic Low-Density Parity Check (QC-LDPC) Codes

Shunliang Mei

Xin Lu

Quasi Cyclic Low Density Parity Check(QC-LDPC) code is an important branch of LDPC code research.It is a kind of constructed LDPC code with check matrix H constructed by quasi cyclic method.IEEE 802.16e proposes a parity check matrix with quasi cyclic character which makes the encoding and hardware easy to be implemented.This article will mainly introduce the encoding process and analyze the decoding performance of various decoding algorithms.Simulations show that Min-Sum(MS) algorithm compares to the Log-BP performance has approximately 0.5dB loss for high-speed rate coding.And the performance of Normalized Min-Sum(NMS) and Row Weight Matched Min-Sum(Rwm-MS) with relatively low complexity is nearly the same as that of Log-BP algorithm.

V. Sh. Le

Rajarshini Mishra

Low-density parity-check (LDPC) have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost , time, power and bandwidth requirements of target applications. Quasi-cyclic low-density parity-check (QC-LDPC) codes are an important subclass of LDPC codes that are known as one of the most effective error controlling methods. Quasi cyclic codes are known to possess some degree of regularity. Many important communication standards such as DVB-S2 and 802.16e use these codes. The proposed Optimized Min-Sum decoding algorithm performs very close to the Sum-Product decoding while preserving the main features of the Min-Sum decoding, that is low complexity and independence with respect to noise variance estimation errors.Proposed decoder is well matched for VLSI implementation and will be implemented on Xilinx FPGA family

nbspAnjitha, nbspProf Sadanandan G K

Kuang-Hao Lin, KyungHi Chang, Chien‐Lin Huang +1 more

In this paper, we construct the cyclic block-type low-density parity-check (CB-LDPC) codes for low complexity hardware implementation. The CB-LDPC code, which is a special class of quasi-cyclic LDPC (QC-LDPC), has an efficient encoding algorithm due to the simple structure of their parity-check matrices. A distribution of irregular parity-check matrix for the CB-LDPC is developed so that we can obtain an area-efficient decoder design, good error correction performance, and low complexity architecture implementation. The CB-LDPC code decoding uses the iterative min-sum algorithm (MSA) and the block parallel connection design to improve the hardware architecture complexity and area.