Introduction of Low-density Parity-Check decoding Algorithm design

Kuang-Hao Lin, Meng-Yi Lin, Jan‐Dong Tseng

In this paper, a modified WiMAX Low-Density Parity-Check (LDPC) codes for realistic LDPC coding system architectures is presented. The LDPC code, which is a special class of quasi-cyclic LDPC (QC-LDPC), has an efficient encoding algorithm owing to the simple structure of their parity-check matrices. A proposed distribution of irregular parity-check matrix for the modified WiMAX LDPC is developed so that we can obtain a low-complexity architecture design, and achievable circuit implementation. The modified WiMAX LDPC code decoding employs the iterative min-sum algorithm (MSA) and its decoder architecture design uses the bit node unit (BNU) and check node unit (CNU). Different word-length of hardware design for LDPC decoder can be simulated. Therefore, the word-length with 8-bit is enough for hardware implementation.

Junho Cho

Ling Zhao, Xiaolin Zhang, Hou Yi

Xinmei Wang

Design of quantized Min-Sum decoder for low-density parity-check (LDPC) codes is very important for the application of LDPC codes.Based on the theory of density evolution,the paper proposes an algorithm to optimize the uniform or ununiform quantized Min-Sum decoder for regular or irregular LDPC codes.Compared with the continuous Sum-Product decoder,the proposed quantized decoder can reduce computational cost with little performance degradation, involving only integer addition calculations.

Naoto Kobayashi, Ryo Nomura, Toshiyasu Matsushima

Kuang-Hao Lin, KyungHi Chang, Sheng-Dong Wu

In this paper, a combined Low-Density Parity-Check (LDPC) code decoding design method, called modified Block-Type LDPC (B-LDPC), for realistic LDPC coding system architectures is presented. The B-LDPC code, which is a special class of quasi-cyclic LDPC (QC-LDPC), has an efficient encoding algorithm owing to the simple structure of their parity-check matrices. A proposed distribution of irregular parity-check matrix for the modified B-LDPC is developed so that we can obtain an area-efficient decoder design, good error correction performance, and achievable architecture implementation. The modified B-LDPC code decoding utilizes the iterative min-sum algorithm (MSA) and its decoding architecture design employs the non-overlapping operations of bit node unit (BNU) and check node unit (CNU). Different block matrix sizes for parity-check matrix can be adopted so that the modified B-LDPC code decoding improves the throughput without obvious performance degradation.