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IET International Conference on Wireless, Mobile and Multimedia Networks (ICWMMN)

Lowering the Error Floor of LDPC Codes Based on Bit-Rectification Strategy

Hui Xue, Lijun Zhang

Published Jan 1, 2019• 0 citations
Publisher
DOI
10.1049/cp.2019.1150

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In weighted bit-flipping-based algorithms for low-density parity-check (LDPC) codes, due to the existence of overconfident incorrectly received bits, the metric values of the corresponding bits will always be wrong in the decoding process. Since these bits cannot be flipped, decoding failure results. To solve this problem, an improved parallel weighted bit flipping algorithm is proposed. Specifically, a reliability-saturation strategy is adopted to increase the flipping probability of the overconfident incorrectly received bits. Simulation results show that the error floor of LDPC codes is greatly lowered.
In this paper, we propose a doping approach to lower the error floor of Low-Density Parity-Check (LDPC) codes. The doping component is a short block code in which the information bits are selected from the coded bits of the dominant trapping sets of the LDPC code. Accordingly, an algorithm for selecting the information bits of the short code is proposed, and a specific two-stage decoding algorithm is presented. Simulation results demonstrate that the proposed doped LDPC code achieves up to 2.0 dB gain compared with the original LDPC code at a frame error rate of 10−6. Furthermore, the proposed design can lower the error floor of original LDPC codes.
One of the most significant impediments to the use of LDPC codes in many communication and storage systems is the error-rate floor phenomenon associated with their iterative decoders. The error floor has been attributed to certain subgraphs of an LDPC codepsilas Tanner graph induced by so-called trapping sets. We show in this paper that once we identify the trapping sets of an LDPC code of interest, a sum-product algorithm (SPA) decoder can be custom-designed to yield floors that are orders of magnitude lower than the conventional SPA decoder. We present three classes of such decoders: (1) a bi-mode decoder, (2) a bit-pinning decoder which utilizes one or more outer algebraic codes, and (3) three generalized-LDPC decoders. We demonstrate the effectiveness of these decoders for two codes, the rate-1/2 (2640,1320) Margulis code which is notorious for its floors and a rate-0.3 (640,192) quasi-cyclic code which has been devised for this study. Although the paper focuses on these two codes, the decoder design techniques presented are fully generalizable to any LDPC code.