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Lowering Error Floor of LDPC Codes: A Machine Learning Approach

Jeongseok Ha, Seokju Han, Kyungmok Oh, Ji Eun Oh

Published Mar 10, 2019• 0 citations
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IET International Conference on Wireless, Mobile and Multimedia Networks (ICWMMN)•Jan 1, 2019•0 citations

A Deep Learning-Aided Post-Processing Scheme to Lower the Error Floor of LDPC Codes

Jiajun He

Low-density parity-check (LDPC) codes are widely used in a variety of communication systems because of their low complexity iterative decoding and performance approaching Shannon capacity. However, the existence of error floor seriously hinders the application and development of LDPC codes in related fields. In this paper, a deep learning-aided post-processing scheme (DLAPPS) based on Layered Normalized Min-Sum algorithm (LNMSA) is proposed to effectively lower error floor of LDPC codes. LNMSA is used in the first stage, and in the second stage incorrect frames are re-decoded by processing two types of nodes classified by neural networks. Simulation results show that the proposed DLAPPS can significantly improve error correction performance and lower the error floor of LDPC codes while maintaining a relatively low decoding complexity.

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Low-density parity-check (LDPC) codes have been successfully commercialized in communication systems due to their strong error correction capabilities and simple decoding process. However, the error-floor phenomenon of LDPC codes, in which the error rate stops decreasing rapidly at a certain level, presents challenges for achieving extremely low error rates and deploying LDPC codes in scenarios demanding ultra-high reliability. In this work, we propose training methods for neural min-sum (NMS) decoders to eliminate the error-floor effect. First, by leveraging the boosting learning technique of ensemble networks, we divide the decoding network into two neural decoders and train the post decoder to be specialized for uncorrected words that the first decoder fails to correct. Secondly, to address the vanishing gradient issue in training, we introduce a block-wise training schedule that locally trains a block of weights while retraining the preceding block. Lastly, we show that assigning different weights to unsatisfied check nodes effectively lowers the error-floor with a minimal number of weights. By applying these training methods to standard LDPC codes, we achieve the best error-floor performance compared to other decoding methods. The proposed NMS decoder, optimized solely through novel training methods without additional modules, can be integrated into existing LDPC decoders without incurring extra hardware costs. The source code is available at https://github.com/ghy1228/LDPC_Error_Floor .

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Parity-Check Matrix Extension to Lower the Error Floors of Irregular LDPC Codes

Jianjun Mu, Xiaopeng Jiao, Jianguang LIU +1 more

Trapping sets have been identified as one of the main factors causing error floors of low-density parity-check (LDPC) codes at high SNR values. By adding several new rows to the original parity-check matrix, a novel method is proposed to eliminate small trapping sets in the LDPC code's Tanner graph. Based on this parity-check matrix extension, we design new codes with low error floors from the original irregular LDPC codes. Simulation results show that the proposed method can lower the error floors of irregular LDPC codes significantly at high SNR values over AWGN channels.

IEICE Transactions on Communications•Jan 1, 2011•1 citation
Low-density parity-check (LDPC) codes are widely used in a variety of communication systems because of their low complexity iterative decoding and performance approaching Shannon capacity. However, the existence of error floor seriously hinders the application and development of LDPC codes in related fields. In this paper, a deep learning-aided post-processing scheme (DLAPPS) based on Layered Normalized Min-Sum algorithm (LNMSA) is proposed to effectively lower error floor of LDPC codes. LNMSA is used in the first stage, and in the second stage incorrect frames are re-decoded by processing two types of nodes classified by neural networks. Simulation results show that the proposed DLAPPS can significantly improve error correction performance and lower the error floor of LDPC codes while maintaining a relatively low decoding complexity.
Low-density parity-check (LDPC) codes have been successfully commercialized in communication systems due to their strong error correction capabilities and simple decoding process. However, the error-floor phenomenon of LDPC codes, in which the error rate stops decreasing rapidly at a certain level, presents challenges for achieving extremely low error rates and deploying LDPC codes in scenarios demanding ultra-high reliability. In this work, we propose training methods for neural min-sum (NMS) decoders to eliminate the error-floor effect. First, by leveraging the boosting learning technique of ensemble networks, we divide the decoding network into two neural decoders and train the post decoder to be specialized for uncorrected words that the first decoder fails to correct. Secondly, to address the vanishing gradient issue in training, we introduce a block-wise training schedule that locally trains a block of weights while retraining the preceding block. Lastly, we show that assigning different weights to unsatisfied check nodes effectively lowers the error-floor with a minimal number of weights. By applying these training methods to standard LDPC codes, we achieve the best error-floor performance compared to other decoding methods. The proposed NMS decoder, optimized solely through novel training methods without additional modules, can be integrated into existing LDPC decoders without incurring extra hardware costs. The source code is available at https://github.com/ghy1228/LDPC_Error_Floor .
Trapping sets have been identified as one of the main factors causing error floors of low-density parity-check (LDPC) codes at high SNR values. By adding several new rows to the original parity-check matrix, a novel method is proposed to eliminate small trapping sets in the LDPC code's Tanner graph. Based on this parity-check matrix extension, we design new codes with low error floors from the original irregular LDPC codes. Simulation results show that the proposed method can lower the error floors of irregular LDPC codes significantly at high SNR values over AWGN channels.