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IEICE Transactions on Electronics

NAND Gate for SFQ Logic Circuits

Hiroaki Myoren, Seiichiro Ono, S. Takada

Published Jan 25, 2000• 1 citation
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We have successfully designed single-flux-quantum (SFQ) universal gates with a wide operating margin. We have previously presented universal gates such as NAND and NOR gates. These universal gates have a small operating margin and should be optimized to realize a wide operating margin. In this study, we newly designed universal gates and optimized the device parameters using an SFQ circuit-optimizing tool. Assuming a 1 kA cm −2 Nb/Al–AlO x /Nb junction technology, the newly designed NAND and NOR gates had a critical margin of more than ±20% for 20 GHz operation. Direct-current bias margins for NAND and NOR gates were also exceeded by ±30% for 20 GHz operation.

Superconductor Science and Technology•Nov 5, 2003•3 citations
In this study, we designed and tested dynamically reconfigurable AND/OR and NAND/NOR single flux quantum (SFQ) logic gates. The measured dc bias margins at low frequency were 99%-126% and 121%-144% for AND/OR and NAND/NOR gates, respectively. The experimentally confirmed maximum operating frequencies of the AND/OR and NAND/NOR gates were 36 and 24 GHz, respectively. We investigated a circuit design method that enables the efficient design of SFQ logic circuits by using dynamically reconfigurable SFQ logic gates. The logic circuits were designed with a small number of gates using the input data pattern dependence of the Boolean function and reconfiguring the dynamically reconfigurable SFQ logic gates. As a case study, we designed and tested a bit-serial SFQ full adder using the investigated circuit design method. Compared with the conventional bit-serial SFQ full adder, the delay of the proposed full adder was reduced by 27%, assuming a clock frequency of 20 GHz. We confirmed correct operation of the adder with a low-speed test.
In this study, we designed and tested dynamically reconfigurable AND/OR and NAND/NOR single flux quantum (SFQ) logic gates. The measured dc bias margins at low frequency were 99%-126% and 121%-144% for AND/OR and NAND/NOR gates, respectively. The experimentally confirmed maximum operating frequencies of the AND/OR and NAND/NOR gates were 36 and 24 GHz, respectively. We investigated a circuit design method that enables the efficient design of SFQ logic circuits by using dynamically reconfigurable SFQ logic gates. The logic circuits were designed with a small number of gates using the input data pattern dependence of the Boolean function and reconfiguring the dynamically reconfigurable SFQ logic gates. As a case study, we designed and tested a bit-serial SFQ full adder using the investigated circuit design method. Compared with the conventional bit-serial SFQ full adder, the delay of the proposed full adder was reduced by 27%, assuming a clock frequency of 20 GHz. We confirmed correct operation of the adder with a low-speed test.
We have successfully designed single-flux-quantum (SFQ) universal gates with a wide operating margin. We have previously presented universal gates such as NAND and NOR gates. These universal gates have a small operating margin and should be optimized to realize a wide operating margin. In this study, we newly designed universal gates and optimized the device parameters using an SFQ circuit-optimizing tool. Assuming a 1 kA cm −2 Nb/Al–AlO x /Nb junction technology, the newly designed NAND and NOR gates had a critical margin of more than ±20% for 20 GHz operation. Direct-current bias margins for NAND and NOR gates were also exceeded by ±30% for 20 GHz operation.