Superconductor Science and Technology

Design of single-flux-quantum universal gates with a wide operating margin

Hiroaki Myoren, Yoshihiro Wakimizu, S. Takada

Published Nov 5, 2003• 3 citations

Abstract

We have successfully designed single-flux-quantum (SFQ) universal gates with a wide operating margin. We have previously presented universal gates such as NAND and NOR gates. These universal gates have a small operating margin and should be optimized to realize a wide operating margin. In this study, we newly designed universal gates and optimized the device parameters using an SFQ circuit-optimizing tool. Assuming a 1 kA cm −2 Nb/Al–AlO x /Nb junction technology, the newly designed NAND and NOR gates had a critical margin of more than ±20% for 20 GHz operation. Direct-current bias margins for NAND and NOR gates were also exceeded by ±30% for 20 GHz operation.

DOI: 10.1088/0953-2048/16/12/028

Related papers

Design Method of Single Flux Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates

Shohei Nishimoto

In this study, we designed and tested dynamically reconfigurable AND/OR and NAND/NOR single flux quantum (SFQ) logic gates. The measured dc bias margins at low frequency were 99%-126% and 121%-144% for AND/OR and NAND/NOR gates, respectively. The experimentally confirmed maximum operating frequencies of the AND/OR and NAND/NOR gates were 36 and 24 GHz, respectively. We investigated a circuit design method that enables the efficient design of SFQ logic circuits by using dynamically reconfigurable SFQ logic gates. The logic circuits were designed with a small number of gates using the input data pattern dependence of the Boolean function and reconfiguring the dynamically reconfigurable SFQ logic gates. As a case study, we designed and tested a bit-serial SFQ full adder using the investigated circuit design method. Compared with the conventional bit-serial SFQ full adder, the delay of the proposed full adder was reduced by 27%, assuming a clock frequency of 20 GHz. We confirmed correct operation of the adder with a low-speed test.

The Japan Society of Applied PhysicsFeb 6, 20140 citations

Design Method of Single-Flux-Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates

Shohei Nishimoto, Yuki Yamanashi, Nobuyuki Yoshikawa

IEEE Transactions on Applied SuperconductivityJan 1, 20159 citations

Design and demonstration of fundamental logic circuits based on a single-flux-quantum gate with a resettable latch

Naoki Takeuchi, A. Akahori, N. Mori +4 more

We have confirmed the importance of the tolerance design for obtaining correct operation in larger-scale Single Flux Quantum (SFQ) logic circuit. Experimental results show that the bias margin of SFQ/dc converter is considerably enhanced by employing tolerance design. The primitives of Single-Flux-Quantum-logic with Ressettable Latch (SFQ-RL) are designed to have high tolerance. As a result, relatively complex circuits based on SFQ-RL including 4-bit Shift Register, 3-Input Majority circuits, binary counter operate correctly with sufficient bias margins. These circuits are fabricated in NEC's standard process using 2.5 kA/cm/sup 2/ Nb/AlOx/Nb junction technology.

IEEE Transactions on Applied SuperconductivityMar 1, 20010 citations

Logic Operation of HTS SFQ Logic Family

Koji Tsubone, Y. Tarutani, H. Wakana +2 more

A high-Tcsuperconducting (HTS) single-flux-quantum (SFQ) logic family including an and gate, an or gate, and an inverter was designed. The circuit parameters were optimized for a Josephson junction's critical current density, which may change due to a temperature change or insufficient run-to-run reproducibility of the fabrication process. New circuit design layout rules were implemented to improve Icx uniformity. As a result, all circuits were successfully tested and show at least plusmn40% critical current density operational margins. An effect of the parasitic capacitance formed by a junction electrode and a ground plane on the operating margins of the and gate was investigated by numerical simulation. Test circuits were fabricated using YBa2Cu3O7-deltaramp-edge junction technology and were operated at temperatures higher than 30 K. Bias current margins were also measured, and they found to be close to the simulated ones.

IEEE Transactions on Applied SuperconductivityJul 15, 20092 citations

Simulation of the Margins in Single Flux Quantum Circuits Containing π-Shifted Josephson Junctions

Yuki Yamanashi, Sotaro Nakaishi, Nobuyuki Yoshikawa

We designed several single flux quantum (SFQ) flip-flops and logic gates composed of Josephson junctions (JJs) and π-shifted JJs (π-JJs) to quantitatively evaluate effectiveness of introduction of π-JJs into the SFQ logic circuit. One-output flip-flops and logic gates were designed on the basis of the circuit design methodology we built for the SFQ circuit containing π-JJs. The designed flip-flops and logic gates have wide operating margins, the dc-bias margins of larger than ±30%, and device parameter margins of ±18%, though the static power consumption are reduced compared to conventional ones composed of JJs. We found that the difference in the critical current density between JJs and π-JJs does not affect the operating margins of the SFQ flip-flop composed of JJs and π-JJs. We devised a circuit structure of the delay flip-flop with complementary outputs composed of JJs and π-JJs (π-DFFC). The analog circuit simulation shows the dc-bias margin of the π-DFFC is larger than ±33%. These results indicate that the large-scale SFQ logic circuit system can be implemented using the flip-flops and logic gates containing π-JJs.

IEEE Transactions on Applied SuperconductivityMar 18, 201911 citations

Design and Verification of SFQ Cell Library for Superconducting LSI Digital Circuits

Xiaoping Gao, Qi Qiao, Mingliang Wang +5 more

We have developed a cell library for superconducting large scale integrated (LSI) digital circuits based on Single Flux Quantum (SFQ) devices. The circuits were designed for a 6-kA/cm2Nb/AlOx/Nb junction process with 10 mask levels including one ground plane and two Nb wiring layers. The initial design and optimization of the circuit parameters were achieved by means of the optimization functions in a circuit simulator, PSCAN2, to ensure that important circuit parameters, Josephson critical current (IC), bias current (Ibias), and inductance satisfied minimal margin requirements. Critical margins of ICand Ibiaswere then further improved manually. To compensate the scattering in the circuit parameters from fabrication by design as much as possible, the critical junction parameters were optimized to further centralize the IC. The library cells were laid out following our design rules determined by systematic experiments on process control monitors (PCM). Basic cells including Josephson transmission lines, splitters, confluence buffers, D flip-flops, T flip-flops, and XOR and NDRO gates were designed, fabricated, and successfully tested at low frequencies. Wide overlaps of the operating regions for the common bias voltages were confirmed.

IEEE Transactions on Applied SuperconductivityMar 11, 202134 citations