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IEEE Transactions on Applied Superconductivity

Simulation of the Margins in Single Flux Quantum Circuits Containing π-Shifted Josephson Junctions

Yuki Yamanashi, Sotaro Nakaishi, Nobuyuki Yoshikawa

Published Mar 18, 2019• 11 citations
Publisher

Abstract

We designed several single flux quantum (SFQ) flip-flops and logic gates composed of Josephson junctions (JJs) and π-shifted JJs (π-JJs) to quantitatively evaluate effectiveness of introduction of π-JJs into the SFQ logic circuit. One-output flip-flops and logic gates were designed on the basis of the circuit design methodology we built for the SFQ circuit containing π-JJs. The designed flip-flops and logic gates have wide operating margins, the dc-bias margins of larger than ±30%, and device parameter margins of ±18%, though the static power consumption are reduced compared to conventional ones composed of JJs. We found that the difference in the critical current density between JJs and π-JJs does not affect the operating margins of the SFQ flip-flop composed of JJs and π-JJs. We devised a circuit structure of the delay flip-flop with complementary outputs composed of JJs and π-JJs (π-DFFC). The analog circuit simulation shows the dc-bias margin of the π-DFFC is larger than ±33%. These results indicate that the large-scale SFQ logic circuit system can be implemented using the flip-flops and logic gates containing π-JJs.

DOI
10.1109/tasc.2019.2904700

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We designed several single flux quantum (SFQ) flip-flops and logic gates composed of Josephson junctions (JJs) and π-shifted JJs (π-JJs) to quantitatively evaluate effectiveness of introduction of π-JJs into the SFQ logic circuit. One-output flip-flops and logic gates were designed on the basis of the circuit design methodology we built for the SFQ circuit containing π-JJs. The designed flip-flops and logic gates have wide operating margins, the dc-bias margins of larger than ±30%, and device parameter margins of ±18%, though the static power consumption are reduced compared to conventional ones composed of JJs. We found that the difference in the critical current density between JJs and π-JJs does not affect the operating margins of the SFQ flip-flop composed of JJs and π-JJs. We devised a circuit structure of the delay flip-flop with complementary outputs composed of JJs and π-JJs (π-DFFC). The analog circuit simulation shows the dc-bias margin of the π-DFFC is larger than ±33%. These results indicate that the large-scale SFQ logic circuit system can be implemented using the flip-flops and logic gates containing π-JJs.
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We present a concept of an advanced rapid single-flux-quantum (RSFQ) logic circuit family using the combination of 0-shifted and π-shifted Josephson junctions. A π-shift in the current-phase relationship can be obtained in several types of Josephson junctions, such as Josephson junctions containing a ferromagnet barrier layer, depending on its thickness and temperature. We use a superconducting quantum interference devices composed of a pair of 0- and π-shifted Josephson junctions (0-π SQUIDs) as a basic circuit element. Unlike the conventional RSFQ logic, bistability is obtained by spontaneous circular currents without using a large superconductor loop, and the state can be flipped by smaller driving currents. These features lead to energy- and/or space-efficient logic gates. In this paper, we show several example circuits where we represent signals by flips of the states of a 0-π SQUID. We obtained successful operation of the circuits from numerical simulation.
Novel reconfigurable superconductive single flux quantum (SFQ) logic devices, the functions of which can be dynamically reconfigured by inputting control signals, have been investigated. The characteristics of single flux quantum circuits can be easily modulated by applying currents or magnetic fields because of the high sensitivity of superconductive circuits. We investigated several design approaches for the realization of dynamically reconfigurable SFQ logic devices. We employed direct current injection to the logic gate using a non-destructive read-out flip-flop. By changing the internal state of the non-destructive read-out flip-flop, the logic function can be dynamically reconfigured. We have designed and tested a dynamically reconfigurable Josephson transmission line (JTL)/delay flip-flop (DFF) circuit. The measured dc bias margin was 72.5-107.2%. Furthermore, we have demonstrated the operation of a variable bit-length shift register, composed of the dynamically reconfigurable JTL/DFF circuits. The investigated design approach can be applied to more sophisticated dynamically reconfigurable single flux quantum logic gates.
Abstract We investigated local magnetic flux biasing (LFB) that induces a phase shift in superconductor circuits by locally applying a magnetic field through the superconductor loop with Josephson junctions. The arbitrary phase shift can be achieved using LFB without modifying the circuit fabrication process. To quantitatively evaluate the effects of introducing LFB for practical superconductor circuit applications, we designed a single flux quantum (SFQ) based non-destructive read-out flip-flop with complementary outputs (NDROC) and a delay flip-flop with complementary outputs (DFFC). The circuit area and static power consumption of the NDROC based on LFB architecture (LFB-NDROC) are approximately 67% and 36% of a conventional NDROC, respectively. The measured bias margin of the LFB-NDROC was in the range of 69%–129%. Using LFB, we were able to reduce the circuit area and power consumption for the DFFC by 67% and 83%, respectively. The measured bias margin of the DFFC with LFB was between 115% and 128%. LFB enabled us to implement a 5-to-32 SFQ decoder which comprises NDROC trees with a reduced circuit area of approximately 60% of a conventional decoder. The results obtained in this study can be applied to not just SFQ circuits but other superconductor circuits also, as they improve the area and power efficiency of such circuits.