Large-scale quantum computers with more than
105 qubits will likely be built within the next decade. Trapped ions, semiconductor devices, and superconducting qubits among other physical implementations are still confined in the realm of medium-scale quantum integration (
∼100 qubits); however, they show promise toward large-scale quantum integration. Building large-scale quantum processing units will require truly scalable control and measurement classical coprocessors as well as suitable wiring methods. In this blue paper, we introduce a fully vertical interconnect that will make it possible to address
∼105 superconducting qubits fabricated on a single silicon or sapphire chip: Pin-chip bonding. This method permits signal transmission from DC to
∼10 GHz, both at room temperature and at cryogenic temperatures down to
∼10 mK. At temperatures below
∼1 K, the on-chip wiring contact resistance is close to zero and all signal lines are in the superconducting state. High-density wiring is achieved by means of a fully vertical interconnect that interfaces the qubit array with a network of rectangular coaxial ribbon cables. Pin-chip bonding is fully compatible with classical high-density test board applications as well as with other qubit implementations.
Scaling superconducting quantum processors to hundreds of qubits is essential for demonstrating quantum advantage and implementing quantum error correction codes with larger distances. A key challenge is integrating control and readout wiring without compromising cryogenic or electronic performance. To address this, we performed a systematic analysis of the thermal budget within a dilution refrigerator and developed high-density 0.5 mm SCuNi-CuNi coaxial cable sets optimized for heat load management. This enables the integration of 696 control lines and 40 readout amplification chains into a dilution refrigerator with a cooling power of 1 mW at 100 mK, maintaining a stable base temperature of ∼8 mK for over a year. We validated the platform's performance with two large-scale quantum processors: a 540-qubit processor with an average T1 of 35 μs and a 156-qubit processor with 182 tunable couplers, achieving average fidelities of 99.9% for single-qubit gates and 99.0% for two-qubit gates. This study demonstrates a viable high-density wiring solution for controlling and measuring processors at the 500-qubit scale and provides critical engineering insights for larger-scale quantum computing systems.
2.5D packaging improves performance and power efficiency due to shorter connectivity distance, enhances signal integrity owing to reduce wiring lengths and higher integration densities. Current technologies cannot provide an integration technique that can handle thousands of single flux quantum devices required for operation. Other criteria include high integration density per chip, a reduced in size for cryogenic cooling system, low-resistance signal pathways, and reliability over cryogenic temperature ranges. 2.5D cryogenic integration approach reduces superconducting computing hardware to a small enough size to fit in a cryogenic chamber. In this publication, we demonstrated the assembly of 2.5D packaging integrating using a 100 um thick superconducting interposer with a qubit chip attached on top and a passive chip on the bottom. Interposer's peripheral is then, die attached and Aluminum (AI) wire bond onto the LTCC substrate