Complex integrated circuits require multiple wiring layers. In complementary metal-oxide-semiconductor processing, these layers are robustly separated by amorphous dielectrics. These dielectrics would dominate energy loss in superconducting integrated circuits. Here, we describe a procedure that capitalizes on the structural benefits of inter-layer dielectrics during fabrication and mitigates the added loss. We use a deposited inter-layer dielectric throughout fabrication and then etch it away post-fabrication. This technique is compatible with foundry level processing and can be generalized to make many different forms of low-loss wiring. We use this technique to create freestanding aluminum vacuum gap crossovers (airbridges). We characterize the added capacitive loss of these airbridges by connecting ground planes over microwave frequency λ/4 coplanar waveguide resonators and measuring resonator loss. We measure a low power resonator loss of ∼3.9 × 10−8 per bridge, which is 100 times lower than that of dielectric supported bridges. We further characterize these airbridges as crossovers, control line jumpers, and as part of a coupling network in gmon and fluxmon qubits. We measure qubit characteristic lifetimes (T1s) in excess of 30 μs in gmon devices.
Dielectric loss from different interfacial layers in the superconducting circuit and from external environment may cause superconducting qubit decoherence. Compared to modeling the entire device at once with a numerical solver, quantitatively formulating the dielectric loss can both describe all loss mechanisms and make the optimization more transparent. In this paper, we first analyze the expression formula of dielectric loss, and obtain a design scheme that can reduce the dielectric loss of qubits. That is, we replace the straight junction wires with the tapered junction wires. Based on this scheme, we perform a simulation to optimize the design of junction wires. Finally, a real experiment is conducted to verify our design. The results show that both the T1 time and T2 time of qubits are significantly improved.
Abstract Three-dimensional device integration facilitates the construction of superconducting quantum information processors with more than several tens of qubits by distributing elements such as control wires, qubits, and resonators between multiple layers. The frequencies of resonators and qubits in flip-chip-bonded multi-chip modules depend on the details of their electromagnetic environment defined by the conductors and dielectrics in their vicinity. Accurate frequency targeting therefore requires precise control of the separation between chips and minimization of their relative tilt. Here, we describe a method to control the inter-chip separation by using polymer spacers. With the spacers, we measure a mean tilt of (76 ± 36) μrad, and a mean deviation of (0.4 ± 0.8) μm from the target inter-chip separation of 10 μm. We apply this process to coplanar waveguide resonator samples and observe chip-to-chip resonator frequency variations below 50 MHz (
≈1% ≈ 1 % ). We measure internal quality factors of
5×105 5 × 10 5 at the single-photon level, suggesting that the added spacers are compatible with low-loss device fabrication.