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Low Complexity High Performance Non-Binary QC-LDPC Decoding System

Sun shulong, Min Lin

Published Dec 9, 2019• 0 citations
Publisher

Abstract

Non-binary LDPC code can achieve better error correcting performance than its binary counterpart especially when the code length is short or moderate. A novel Non-Binary LDPC code is presented in this paper to replace the traditional binary standard in 802.11n system. The proposed Parity Check Matrix (PCM) is optimized by eliminating short-girths and low weight code-words. Partially-parallel quasi-cyclic structure is adopted for the encoder and the check matrix is quasi diagonal line structure. Encoding process directly utilizes check matrix rather than generator matrix to generate check sequence. For decoding process, the (Forward Backward Extended Minimum Sum (FB-EMS) algorithm is adopted. The performance of the proposed Non-binary LDPC code over GF(16) shows more than 1dB coding gain at 10^(-6) BER compared to the traditional binary standard with same bit length for 802.11n standard. Encoder structure and decoder algorithm have been also presented. For practical purposes, this Non-binary quasi-cyclic LDPC code with low complexity makes our proposed system very attractive.

DOI
10.33969/eecs.v3.034

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Non-binary LDPC code can achieve better error correcting performance than its binary counterpart especially when the code length is short or moderate. A novel Non-Binary LDPC code is presented in this paper to replace the traditional binary standard in 802.11n system. The proposed Parity Check Matrix (PCM) is optimized by eliminating short-girths and low weight code-words. Partially-parallel quasi-cyclic structure is adopted for the encoder and the check matrix is quasi diagonal line structure. Encoding process directly utilizes check matrix rather than generator matrix to generate check sequence. For decoding process, the (Forward Backward Extended Minimum Sum (FB-EMS) algorithm is adopted. The performance of the proposed Non-binary LDPC code over GF(16) shows more than 1dB coding gain at 10^(-6) BER compared to the traditional binary standard with same bit length for 802.11n standard. Encoder structure and decoder algorithm have been also presented. For practical purposes, this Non-binary quasi-cyclic LDPC code with low complexity makes our proposed system very attractive.
Next generation wireless systems, such as IEEE802.11n and 802.16e, need high error-correction capacity to achieve high data rate transmission. Therefore, a low-density parity-check code(LDPC code) is adopted as a FEC code. Quasi-cyclic LDPC code(QC-LDPC) code is an important branch of LDPC code research. IEEE 802.16e proposes a parity-check matrix with quasi-cyclic character which makes the encoding very simply. This paper introduces the encoding process and several decoding algorithms for LDPC including Log-BP algorithm, Min-Sum(MS) algorithm and modified MS algorithm. Simulations results under a next generation wireless LAN system show that MS comparing with the Log-BP performance has approximately 0.5dB loss for high-speed rates codes over AWGN channel, however the performance of normalized MS and row weight matched MS with relatively low complexity is nearly the same as that of Log-BP algorithm.
Non-binary LDPC (NB-LDPC) codes has inherent parallelism and excellent error correcting performance. By comparing with other traditional algorithm, FFT-SPA based non-binary LDPC code gives reduced computation complexity with better decoding performance. In this paper, FFT-SPA based NB-LDPC decoding performance is analyzed for the specification of IEEE 802.11n standard. Parity check matrix (PCM) defines the strength of the LDPC codes. By retaining the properties of the PCM structures, in this paper we propose two modified parity check matrices to reduce the computation strength. For various order of Galois Field with different PCM structures, non-binary LDPC codes performances are analyzed.
Non-Binary Low-Density-Parity-Check codes (NB-LDPC) have shown superior performance but its huge complexity and low throughput prevent it from practical applications. This paper presents a novel architecture to implement a kind of high-throughput low-complexity irregular quasi-cyclic NB-LDPC decoder over GF (16) based on Extended Min-Sum (EMS) Algorithm. Double clocks are adopted in this paper. The low frequency clock at 60 MHz serves as the system clock and the high frequency clock at 480 MHz works for check nodes and variable nodes thus they can be reused 8 times during one system clock period as a result the complexity can be largely reduced. Synthesis result shows that the throughput can achieve 68.57 Mbps at 5 iterations. FPGA testing result shows that the decoder has little performance degradation compared with its floating model and it can provide about 0.5 dB coding gain compared with its binary LDPC code of the same block length. The proposed architecture can be conveniently extended to higher Galois Filed such as GF (64) or GF (256) and it can be applied for different code length and rate by modifying a slight part of the decoder. Compared with previous works, the decoder proposed in this paper is more efficient for practical applications.
Quasi Cyclic Low Density Parity Check(QC-LDPC) code is an important branch of LDPC code research.It is a kind of constructed LDPC code with check matrix H constructed by quasi cyclic method.IEEE 802.16e proposes a parity check matrix with quasi cyclic character which makes the encoding and hardware easy to be implemented.This article will mainly introduce the encoding process and analyze the decoding performance of various decoding algorithms.Simulations show that Min-Sum(MS) algorithm compares to the Log-BP performance has approximately 0.5dB loss for high-speed rate coding.And the performance of Normalized Min-Sum(NMS) and Row Weight Matched Min-Sum(Rwm-MS) with relatively low complexity is nearly the same as that of Log-BP algorithm.
Non-binary (NB) low-density parity-check (LDPC) codes offer superior error-correcting performance compared to binary LDPC codes, especially for short and medium lengths. Constructing such codes with large girth remains challenging due to various combinatorial constraints. We present a novel algebraic and graph-theoretic construction of non-binary quasi-cyclic (QC) LDPC codes with column weight two and girth 12, which is known to be largest achievable girth for array-based QC-LDPC codes. In constructing girth-12 (2, dc) NB-QC-LDPC codes, our method attains the minimum possible code length for dc < 10. Motivated by the fact that non-binary spatially coupled (SC) QC-LDPC codes achieve optimal performance at column weight three, we further construct NB-SC-QC-LDPC codes with girth ≥ 8 while effectively reducing the number of 8-cycles. Specifically, for (3, dc) codes, our design eliminates dominant absorbing sets such as the (3, 3) and (4, 2), eliminates the (5, 1) elementary absorbing sets (EAS), and eliminates almost all (6, 2) EAS, thereby directly enhancing the error-correction performance. The proposed NB-QC-LDPC codes achieve performance comparable to NB-LDPC codes used in the BeiDou satellite navigation system, while requiring a significantly smaller parity-check matrix storage footprint, for instance, around a 44× reduction in storage requirements with respect to BeiDou rate-1/2 (88, 44) code. Also, the proposed rate-1/2 code with length n = 684 provide a 0.4 dB gain over non-binary near-regular QC-LDPC code with same parameters proposed by Huang et al. [IEEE Trans. Commun.] while requiring a smaller parity-check matrix storage footprint. Furthermore, the proposed rate-1/2 NB-SC-QC-LDPC code having length n = 4608 achieve 0.1 dB coding gain compared to existing protograph constructions while requiring a significantly smaller parity-check matrix storage footprint, i.e., around a 192× reduction.