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International Conference on Intelligent Computation Technology and Automation

Analysis on QC-LDPC Decoding Algorithms for WLAN Systems

Xin Lu, Zhan Shaobin, Xu Jiong

Published May 1, 2010• 2 citations
Publisher

Abstract

Next generation wireless systems, such as IEEE802.11n and 802.16e, need high error-correction capacity to achieve high data rate transmission. Therefore, a low-density parity-check code(LDPC code) is adopted as a FEC code. Quasi-cyclic LDPC code(QC-LDPC) code is an important branch of LDPC code research. IEEE 802.16e proposes a parity-check matrix with quasi-cyclic character which makes the encoding very simply. This paper introduces the encoding process and several decoding algorithms for LDPC including Log-BP algorithm, Min-Sum(MS) algorithm and modified MS algorithm. Simulations results under a next generation wireless LAN system show that MS comparing with the Log-BP performance has approximately 0.5dB loss for high-speed rates codes over AWGN channel, however the performance of normalized MS and row weight matched MS with relatively low complexity is nearly the same as that of Log-BP algorithm.

DOI
10.1109/icicta.2010.820

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Next generation wireless systems, such as IEEE802.11n and 802.16e, need high error-correction capacity to achieve high data rate transmission. Therefore, a low-density parity-check code(LDPC code) is adopted as a FEC code. Quasi-cyclic LDPC code(QC-LDPC) code is an important branch of LDPC code research. IEEE 802.16e proposes a parity-check matrix with quasi-cyclic character which makes the encoding very simply. This paper introduces the encoding process and several decoding algorithms for LDPC including Log-BP algorithm, Min-Sum(MS) algorithm and modified MS algorithm. Simulations results under a next generation wireless LAN system show that MS comparing with the Log-BP performance has approximately 0.5dB loss for high-speed rates codes over AWGN channel, however the performance of normalized MS and row weight matched MS with relatively low complexity is nearly the same as that of Log-BP algorithm.
Quasi Cyclic Low Density Parity Check(QC-LDPC) code is an important branch of LDPC code research.It is a kind of constructed LDPC code with check matrix H constructed by quasi cyclic method.IEEE 802.16e proposes a parity check matrix with quasi cyclic character which makes the encoding and hardware easy to be implemented.This article will mainly introduce the encoding process and analyze the decoding performance of various decoding algorithms.Simulations show that Min-Sum(MS) algorithm compares to the Log-BP performance has approximately 0.5dB loss for high-speed rate coding.And the performance of Normalized Min-Sum(NMS) and Row Weight Matched Min-Sum(Rwm-MS) with relatively low complexity is nearly the same as that of Log-BP algorithm.
Non-binary LDPC code can achieve better error correcting performance than its binary counterpart especially when the code length is short or moderate. A novel Non-Binary LDPC code is presented in this paper to replace the traditional binary standard in 802.11n system. The proposed Parity Check Matrix (PCM) is optimized by eliminating short-girths and low weight code-words. Partially-parallel quasi-cyclic structure is adopted for the encoder and the check matrix is quasi diagonal line structure. Encoding process directly utilizes check matrix rather than generator matrix to generate check sequence. For decoding process, the (Forward Backward Extended Minimum Sum (FB-EMS) algorithm is adopted. The performance of the proposed Non-binary LDPC code over GF(16) shows more than 1dB coding gain at 10^(-6) BER compared to the traditional binary standard with same bit length for 802.11n standard. Encoder structure and decoder algorithm have been also presented. For practical purposes, this Non-binary quasi-cyclic LDPC code with low complexity makes our proposed system very attractive.
Low-density parity-check (LDPC) have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost , time, power and bandwidth requirements of target applications. Quasi-cyclic low-density parity-check (QC-LDPC) codes are an important subclass of LDPC codes that are known as one of the most effective error controlling methods. Quasi cyclic codes are known to possess some degree of regularity. Many important communication standards such as DVB-S2 and 802.16e use these codes. The proposed Optimized Min-Sum decoding algorithm performs very close to the Sum-Product decoding while preserving the main features of the Min-Sum decoding, that is low complexity and independence with respect to noise variance estimation errors.Proposed decoder is well matched for VLSI implementation and will be implemented on Xilinx FPGA family
Through the research on the decoding algorithm of low-density parity-check (LDPC) code, a low complexity decoding algorithm suitable for quasi-cyclic LDPC (QC-LDPC) code is proposed in this paper. The algorithm adopts layered decoding (LD), and the sub-minimum is replaced by the sum of an optimal correction factor and the minimum during the process of the check nodes update. Therefore, it is not required to find the sub-minimum and the computational complexity reduces significantly. Matlab simulation results show that the decoding performance of this algorithm is very near to min-sum (MS) algorithm, and more superior than single min-sum (SMS) algorithm.
Most quasi-cyclic LDPC codes decoders of IEEE 802.11n and IEEE 802.16e standards adopt Layered decoding algorithm recently. A fast double layered decoding algorithm for quasi-cyclic LDPC codes in which two row groupings of check nodes are processed synchronously in order to speed the decoding processing is proposed. Compared to BP algorithm and normal Layered decoding algorithm, the proposed algorithm provides a faster decoding speed and more favorable tradeoffs among complexity, decoding speed and error correcting performance. Simulation results show validity and efficiency of the proposed decoding algorithm.
This paper presents a different decoding techniques for Quasi-Cyclic (QC) Low Density Parity Check (LDPC) code. QC-LDPC code is proposed to reduce the complexity of the Low Density Parity Check code while obtaining the similar performance. The encoding and decoding processes of these codes are easy to simplify and implement. The algorithm used for encoding and decoding are based on matrices and implemented on MATLAB for simulation results. In this paper decoding technique QC-LDPC is introduced and compare the performance of LDPC and QC-LDPC. The decoding techniques is conducted by different algorithms such as Bit Flipping (BF), Belief Propagation (BP) Log, Belief Propagation (BP) Probabilistic (Prob), Belief Propagation (BP) Log Simple.