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Pacific-Asia Conference on Circuits, Communications and Systems

A Fast Double Layered Decoding Algorithm for Quasi-Cyclic LDPC Codes

Zhixiong Chen, Jinsha Yuan

Published May 1, 2009• 0 citations
Publisher

Abstract

Most quasi-cyclic LDPC codes decoders of IEEE 802.11n and IEEE 802.16e standards adopt Layered decoding algorithm recently. A fast double layered decoding algorithm for quasi-cyclic LDPC codes in which two row groupings of check nodes are processed synchronously in order to speed the decoding processing is proposed. Compared to BP algorithm and normal Layered decoding algorithm, the proposed algorithm provides a faster decoding speed and more favorable tradeoffs among complexity, decoding speed and error correcting performance. Simulation results show validity and efficiency of the proposed decoding algorithm.

DOI
10.1109/paccs.2009.143

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Most quasi-cyclic LDPC codes decoders of IEEE 802.11n and IEEE 802.16e standards adopt Layered decoding algorithm recently. A fast double layered decoding algorithm for quasi-cyclic LDPC codes in which two row groupings of check nodes are processed synchronously in order to speed the decoding processing is proposed. Compared to BP algorithm and normal Layered decoding algorithm, the proposed algorithm provides a faster decoding speed and more favorable tradeoffs among complexity, decoding speed and error correcting performance. Simulation results show validity and efficiency of the proposed decoding algorithm.
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A multi-rate decoder of Quasi-Cyclic LDPC(QC-LDPC) decoder is presented based on the improvement of layered decoding algorithm.The implementation has larger bit throughput resulting from fast convergence speed by more than 50 percent in terms of decoding iterations.Only four memories are used to store the messages which significantly reduce the area and the power dissipation.Adjusted integer quantization of layered decoding algorithm for check-node updating reduces the complexity and the correction factor guarantees the error rate performance.The proposed decoding architecture is implemented in the standard recommended.The decoder consumes 0.6 million gates,and reaches a throughput of 134 Mb/s at a clock frequency of 110 MHz with rate of 1/2.
Entering the 5G era, the hardware design of low-density parity-check (LDPC) codes under the new standard has increasingly higher requirements on throughput. According to the geometric characteristics of the check matrices of the quasi-cyclicQC) LDCP codes under the CCSDS standard, this paper designs a layered dynamic normalized minimum sum algorithm(LDNMSA) under the pre-termination decoding based on de-layering scheme. The check matrix structure of this code is easy for hardware design and the storage resource consumption is low. The approximate replacement of the minimum sum algorithm(MSA) reduces the computational complexity of the check node update process. The determination of correction factors and inter-layer deletion thresholds through computer simulation improves the decoding performance and the speed of a single iteration, and adopt the layered scheduling scheme with optimized update order reduces the number of iterations required for decoding. Experimental results show that when the bit error rate(BER) is 10-5, the designed algorithm has a gain of approximately 0.5 dB compared to the MSA. The speed and calculation amounts to a single iteration are much lower than the log-likelihood-ratio(LLR) belief propagation(BP) algorithm and the performance is only less than 0.1dB.
Through the research on the decoding algorithm of low-density parity-check (LDPC) code, a low complexity decoding algorithm suitable for quasi-cyclic LDPC (QC-LDPC) code is proposed in this paper. The algorithm adopts layered decoding (LD), and the sub-minimum is replaced by the sum of an optimal correction factor and the minimum during the process of the check nodes update. Therefore, it is not required to find the sub-minimum and the computational complexity reduces significantly. Matlab simulation results show that the decoding performance of this algorithm is very near to min-sum (MS) algorithm, and more superior than single min-sum (SMS) algorithm.
A new fast decoding method of Quasi-Cyclic LDPC(QC-LDPC)codes, named semi-serial decoding algorithm, is presented through contraposing the shortcoming of flood decoding method.For the algorithm, the message was updated in a serial sequence of m subsets of check nodes(or variable nodes), while the check nodes(or variable nodes) in the same subset are updated simultaneously. In this way,the decoding speed would be faster than the common serial decoding algorithm several times. An efficient grouping method suitable for the quasi-cyclic LDPC codes based on the circulant architecture is proposed.Simulation results show that,under the same complexiry,the proposed algorithm fastens the decoding speed of quasi-cyclic LDPC codes, meanwhile, it inherits all the merits of the serial massage-passing decoding algorithm. The conclusion is that the speed of the semi-serial decoding method is at least p times than that of the serial one(p is the number of rows of the cyclic permutation matrix in the parity check matrix of quasi-cyclic LDPC codes).
Quasi Cyclic Low Density Parity Check(QC-LDPC) code is an important branch of LDPC code research.It is a kind of constructed LDPC code with check matrix H constructed by quasi cyclic method.IEEE 802.16e proposes a parity check matrix with quasi cyclic character which makes the encoding and hardware easy to be implemented.This article will mainly introduce the encoding process and analyze the decoding performance of various decoding algorithms.Simulations show that Min-Sum(MS) algorithm compares to the Log-BP performance has approximately 0.5dB loss for high-speed rate coding.And the performance of Normalized Min-Sum(NMS) and Row Weight Matched Min-Sum(Rwm-MS) with relatively low complexity is nearly the same as that of Log-BP algorithm.