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Journal of Shenzhen Institute of Information Technology

Analysis of QC-LDPC codes in IEEE 802.16e

Xin Lu

Published Jan 1, 2009• 0 citations
OpenAlex

Abstract

Quasi Cyclic Low Density Parity Check(QC-LDPC) code is an important branch of LDPC code research.It is a kind of constructed LDPC code with check matrix H constructed by quasi cyclic method.IEEE 802.16e proposes a parity check matrix with quasi cyclic character which makes the encoding and hardware easy to be implemented.This article will mainly introduce the encoding process and analyze the decoding performance of various decoding algorithms.Simulations show that Min-Sum(MS) algorithm compares to the Log-BP performance has approximately 0.5dB loss for high-speed rate coding.And the performance of Normalized Min-Sum(NMS) and Row Weight Matched Min-Sum(Rwm-MS) with relatively low complexity is nearly the same as that of Log-BP algorithm.

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Quasi Cyclic Low Density Parity Check(QC-LDPC) code is an important branch of LDPC code research.It is a kind of constructed LDPC code with check matrix H constructed by quasi cyclic method.IEEE 802.16e proposes a parity check matrix with quasi cyclic character which makes the encoding and hardware easy to be implemented.This article will mainly introduce the encoding process and analyze the decoding performance of various decoding algorithms.Simulations show that Min-Sum(MS) algorithm compares to the Log-BP performance has approximately 0.5dB loss for high-speed rate coding.And the performance of Normalized Min-Sum(NMS) and Row Weight Matched Min-Sum(Rwm-MS) with relatively low complexity is nearly the same as that of Log-BP algorithm.
Next generation wireless systems, such as IEEE802.11n and 802.16e, need high error-correction capacity to achieve high data rate transmission. Therefore, a low-density parity-check code(LDPC code) is adopted as a FEC code. Quasi-cyclic LDPC code(QC-LDPC) code is an important branch of LDPC code research. IEEE 802.16e proposes a parity-check matrix with quasi-cyclic character which makes the encoding very simply. This paper introduces the encoding process and several decoding algorithms for LDPC including Log-BP algorithm, Min-Sum(MS) algorithm and modified MS algorithm. Simulations results under a next generation wireless LAN system show that MS comparing with the Log-BP performance has approximately 0.5dB loss for high-speed rates codes over AWGN channel, however the performance of normalized MS and row weight matched MS with relatively low complexity is nearly the same as that of Log-BP algorithm.
Low-density parity-check (LDPC) have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost , time, power and bandwidth requirements of target applications. Quasi-cyclic low-density parity-check (QC-LDPC) codes are an important subclass of LDPC codes that are known as one of the most effective error controlling methods. Quasi cyclic codes are known to possess some degree of regularity. Many important communication standards such as DVB-S2 and 802.16e use these codes. The proposed Optimized Min-Sum decoding algorithm performs very close to the Sum-Product decoding while preserving the main features of the Min-Sum decoding, that is low complexity and independence with respect to noise variance estimation errors.Proposed decoder is well matched for VLSI implementation and will be implemented on Xilinx FPGA family
This paper presents a different decoding techniques for Quasi-Cyclic (QC) Low Density Parity Check (LDPC) code. QC-LDPC code is proposed to reduce the complexity of the Low Density Parity Check code while obtaining the similar performance. The encoding and decoding processes of these codes are easy to simplify and implement. The algorithm used for encoding and decoding are based on matrices and implemented on MATLAB for simulation results. In this paper decoding technique QC-LDPC is introduced and compare the performance of LDPC and QC-LDPC. The decoding techniques is conducted by different algorithms such as Bit Flipping (BF), Belief Propagation (BP) Log, Belief Propagation (BP) Probabilistic (Prob), Belief Propagation (BP) Log Simple.
Through the research on the decoding algorithm of low-density parity-check (LDPC) code, a low complexity decoding algorithm suitable for quasi-cyclic LDPC (QC-LDPC) code is proposed in this paper. The algorithm adopts layered decoding (LD), and the sub-minimum is replaced by the sum of an optimal correction factor and the minimum during the process of the check nodes update. Therefore, it is not required to find the sub-minimum and the computational complexity reduces significantly. Matlab simulation results show that the decoding performance of this algorithm is very near to min-sum (MS) algorithm, and more superior than single min-sum (SMS) algorithm.
In this paper, we construct the cyclic block-type low-density parity-check (CB-LDPC) codes for low complexity hardware implementation. The CB-LDPC code, which is a special class of quasi-cyclic LDPC (QC-LDPC), has an efficient encoding algorithm due to the simple structure of their parity-check matrices. A distribution of irregular parity-check matrix for the CB-LDPC is developed so that we can obtain an area-efficient decoder design, good error correction performance, and low complexity architecture implementation. The CB-LDPC code decoding uses the iterative min-sum algorithm (MSA) and the block parallel connection design to improve the hardware architecture complexity and area.
This paper presents Bit error Rate performance Analysis of Quasi Cyclic Low Density Parity Check Codes (QC-LDPC) with girth 6 using Log Domain sum product and Simple Log Domain Sum Product Algorithm for Decoding. The approach to construct Parity Check matrix for LDPC codes is based on sparse Lower Upper decomposition. Then to create QC-LDPC matrix counter shifting, interleave mapping, Set XORing, Circulant Shifting and Randomization processes are being used. The constructed QC-LDPC codes is of a girth 6 on / code Rate have row weight 6 and column weight 3. Bit error rate performance is done through simulation to be calculated for various code length such as code I (960, 480), code II (1980, 990) and code III (1080, 540).