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TECHNOLOGY IMPLEMENTATION OF DIFFERENT DECODING TECHNIQUES FOR QUASI CYCLIC LOW DENSITY PARITY CHECK CODES (QC-LDPC)

Geeta Arora

Published Jan 1, 2015• 0 citations
OpenAlex

Abstract

This paper presents a different decoding techniques for Quasi-Cyclic (QC) Low Density Parity Check (LDPC) code. QC-LDPC code is proposed to reduce the complexity of the Low Density Parity Check code while obtaining the similar performance. The encoding and decoding processes of these codes are easy to simplify and implement. The algorithm used for encoding and decoding are based on matrices and implemented on MATLAB for simulation results. In this paper decoding technique QC-LDPC is introduced and compare the performance of LDPC and QC-LDPC. The decoding techniques is conducted by different algorithms such as Bit Flipping (BF), Belief Propagation (BP) Log, Belief Propagation (BP) Probabilistic (Prob), Belief Propagation (BP) Log Simple.

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•Sep 8, 2020•1 citation
This paper presents a different decoding techniques for Quasi-Cyclic (QC) Low Density Parity Check (LDPC) code. QC-LDPC code is proposed to reduce the complexity of the Low Density Parity Check code while obtaining the similar performance. The encoding and decoding processes of these codes are easy to simplify and implement. The algorithm used for encoding and decoding are based on matrices and implemented on MATLAB for simulation results. In this paper decoding technique QC-LDPC is introduced and compare the performance of LDPC and QC-LDPC. The decoding techniques is conducted by different algorithms such as Bit Flipping (BF), Belief Propagation (BP) Log, Belief Propagation (BP) Probabilistic (Prob), Belief Propagation (BP) Log Simple.
Quasi Cyclic Low Density Parity Check(QC-LDPC) code is an important branch of LDPC code research.It is a kind of constructed LDPC code with check matrix H constructed by quasi cyclic method.IEEE 802.16e proposes a parity check matrix with quasi cyclic character which makes the encoding and hardware easy to be implemented.This article will mainly introduce the encoding process and analyze the decoding performance of various decoding algorithms.Simulations show that Min-Sum(MS) algorithm compares to the Log-BP performance has approximately 0.5dB loss for high-speed rate coding.And the performance of Normalized Min-Sum(NMS) and Row Weight Matched Min-Sum(Rwm-MS) with relatively low complexity is nearly the same as that of Log-BP algorithm.
Next generation wireless systems, such as IEEE802.11n and 802.16e, need high error-correction capacity to achieve high data rate transmission. Therefore, a low-density parity-check code(LDPC code) is adopted as a FEC code. Quasi-cyclic LDPC code(QC-LDPC) code is an important branch of LDPC code research. IEEE 802.16e proposes a parity-check matrix with quasi-cyclic character which makes the encoding very simply. This paper introduces the encoding process and several decoding algorithms for LDPC including Log-BP algorithm, Min-Sum(MS) algorithm and modified MS algorithm. Simulations results under a next generation wireless LAN system show that MS comparing with the Log-BP performance has approximately 0.5dB loss for high-speed rates codes over AWGN channel, however the performance of normalized MS and row weight matched MS with relatively low complexity is nearly the same as that of Log-BP algorithm.
The non-binary LDPC is the promotion to the finite GF(q) of binary LDPC codes.The parity check matrix elements is no longer 0 and 1,but collections(0,1,2,…,q-1),while the decoding still uses the efficient iterative decoding based on belief propagation algorithm.This paper focuses on the check matrix of structure of the quasi-cyclic LDPC codes(QC-LDPC) as well as the min-sum decoding algorithm.Then the LDPC codes decoding performance is simulated under different conditions in white Gaussian noise channel(AWGN) with Matlab.Finally,the impact of non-binary LDPC Decoding performance factors is analyzed.
This paper presents a reduced-complexity iterative decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes which is devised based on the section-wise cyclic structure of their parity-check matrices. The decoding scheme significantly reduces the hardware implementation complexity of a QC-LDPC code decoder in terms of the number of message processing units and the number of wires required to connect the message processing units. A long high-rate high-performance QC-LDPC code is used to demonstrate the effectiveness of the proposed decoding scheme. Using this long code as the mother code, descendant QC-LDPC codes of various lengths and rates can be constructed by puncturing and masking the columns and rows of the parity-check matrix of the mother code. These descendant codes can be decoded by deactivating specific sets of message processing units of the mother decoder.
In this paper, we construct the cyclic block-type low-density parity-check (CB-LDPC) codes for low complexity hardware implementation. The CB-LDPC code, which is a special class of quasi-cyclic LDPC (QC-LDPC), has an efficient encoding algorithm due to the simple structure of their parity-check matrices. A distribution of irregular parity-check matrix for the CB-LDPC is developed so that we can obtain an area-efficient decoder design, good error correction performance, and low complexity architecture implementation. The CB-LDPC code decoding uses the iterative min-sum algorithm (MSA) and the block parallel connection design to improve the hardware architecture complexity and area.
Abstract Layered decoding (LD) of Low-Density Parity-Check (LDPC) codes is a decoding schedule that facilitates partially parallel architectures for performing Belief Propagation (BP)-based iterative algorithms. It has reduced implementation complexity and memory overhead compared to fully parallel architectures and higher convergence speed compared to both serial and parallel architectures. In this paper, we introduce a modified form of shuffling of the Parity-Check Matrices (PCMs) of Quasi-Cyclic LDPC (QC-LDPC) codes, which is basically an interleaving operation of the rows of the PCM. The modified shuffling method just like the conventional shuffling method results in a PCM in which each layer can be produced by the circulation of its above layer one symbol to the right. However, it additionally guarantees the weights of the columns in each layer to be either zero or one. Then, we show that due to these two properties, the number of occupied Look-Up Tables (LUTs) on a Field Programmable Gate Array (FPGA) is reduced by about 93% and consumed on-chip power by nearly 80%. Nevertheless, shuffling doesn’t degrade Bit Error Rate (BER) performance compared with the non-shuffled case. Additionally, decoding throughput is not sacrificed for low SNR values and its degradation is negligible until the BER of 1e-6.