Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

International Conference on Computing, Electronics & Communications Engineering (iCCECE)

A Low Complexity Decoding Algorithm Design Based on Quasi-Cyclic LDPC Codes

Cai Honghao, Yingkun Yang, Yi Qu

Published Aug 17, 2020• 2 citations
Publisher

Abstract

Entering the 5G era, the hardware design of low-density parity-check (LDPC) codes under the new standard has increasingly higher requirements on throughput. According to the geometric characteristics of the check matrices of the quasi-cyclicQC) LDCP codes under the CCSDS standard, this paper designs a layered dynamic normalized minimum sum algorithm(LDNMSA) under the pre-termination decoding based on de-layering scheme. The check matrix structure of this code is easy for hardware design and the storage resource consumption is low. The approximate replacement of the minimum sum algorithm(MSA) reduces the computational complexity of the check node update process. The determination of correction factors and inter-layer deletion thresholds through computer simulation improves the decoding performance and the speed of a single iteration, and adopt the layered scheduling scheme with optimized update order reduces the number of iterations required for decoding. Experimental results show that when the bit error rate(BER) is 10-5, the designed algorithm has a gain of approximately 0.5 dB compared to the MSA. The speed and calculation amounts to a single iteration are much lower than the log-likelihood-ratio(LLR) belief propagation(BP) algorithm and the performance is only less than 0.1dB.

DOI
10.1109/iccece49321.2020.9231083

Related papers

Reduced-Complexity Belief Propagation Decoding for LDPC Codes

Heping Wan, Joonyoung Cho, Min Jang +1 more

Two methods are proposed to reduce the complexity of the belief propagation (BP) decoding for low-density parity-check (LDPC) codes, with the focus on the layered decoding for quasi-cyclic LDPC (QC-LDPC) codes. The two methods can be separately incorporated into the layered decoding procedures and combined seamlessly to provide the two-fold complexity reduction. In the first method, the message updates regarding a subset of variable nodes are omitted. To construct the subset, the most reliable bit-level channels, derived fromM-ary input channels, are identified. Then, we select the variable nodes with initial log-likelihood ratios (LLRs) exceeding a threshold among the ones assigned to the most reliable bit-level channels to form the subset. The threshold is designed and adjusted based on characteristics of the most reliable bit-level channels. Our numerical results demonstrate that the first method significantly reduces the complexity with negligibly impacting the error-correcting performance. In the second method, each layer of base graphs of QC-LDPC codes uses either sum-product algorithm (SPA) or min-sum algorithm (MSA) to update LLRs. A degree-based algorithm is presented to determine the layers employing either SPA or MSA. We compare with two intuitive methods: 1) applying SPA to randomly selected layers and MSA to the remaining layers, and 2) applying SPA to the core layers of 5G NR LDPC codes and MSA to the remaining layers. According to the numerical results, the degree-based algorithm maximally reduces the complexity while maintaining the same performance. To evaluate the joint method, the first method is applied on top of the second method. Further complexity reduction is achieved without degrading the performance of the second method.

IEEE Access•Jan 1, 2026•0 citations

Improved Layered Minimum Sum Decoding Algorithm Based on Overestimation

Liu Yu, Lin Bai, Yaohui Hao

Quasi-cyclic low-density parity-check (QC-LDPC) codes are linear block codes with performance close to the Shannon limit. The layered minimum sum (LMS) decoding algorithm speeds up the decoding convergence by layering the check matrix and updating the nodes according to the layers. However, the MS algorithm has the problem of over estimation and affects the decoding performance due to its simplified strategy of MS algorithm updating the message of check nodes. Therefore, this paper proposes a layered minimum sum decoding algorithm based on overestimation. By setting the correction threshold and updating the check nodes by the conditions, the decoding performance is improved. When the code length is 2048 and the bit error rate is , the proposed algorithm can improve the decoding convergence speed by about 25% and obtain a coding gain of about 0.1 dB.

•Sep 23, 2022•0 citations

A Second Minimum Approximation Method for Layered Min-Sum Decoding of QC-LDPC Codes

Zijian Qin, Yangcan Zhou, Zhongfeng Wang

Low-density parity-check (LDPC) codes have attracted tremendous attention for their excellent error-correction performance and inherent fitness for high-parallelism implementation. With great complexity reduction and friendly for hardware implementation, the min-sum (MS) decoding algorithm for LDPC codes gains widespread applications in practical. In the MS decoding algorithm, finding the first two minima among input variable-to-check messages is the most complex part. To further reduce the complexity of the MS decoding algorithm, an efficient single-minimum (single-min) based layered MS decoding for quasi-cyclic LDPC (QC-LDPC) codes is proposed in this paper. It is found that statistically the difference between the first minimum and second minimum increases as the decoding becomes more convergent. Accordingly, in the proposed single-min scheme, the second minimum is approximately derived based on the first minimum and an index indicating the convergence degree. Besides, some other metrics that are easily obtained are used to refine the second minimum. Simulation results show that the proposed method can significantly improve the error-correction performance and lower the average number of iterations, compared with the state-of-the-art single-min based MS decoding algorithms.

Information Communication Technologies Conference (ICTC)•May 17, 2023•1 citation

A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio

Anuj Verma, Rahul Shrestha

This paper presents partially-parallel low-density parity-check (LDPC) decoder architecture for binary-input additive-white Gaussian-noise (BIAWGN) channel in 5G new-radio cellular-communication technology based on layered min-sum decoding algorithm. This architecture exploits the iterative decomposition of check-node and variable-node combined-processing unit which leads to area optimization and lower hardware complexity. The proposed VLSI architecture of LDPC decoder processes quasi-cyclic LDPC encoded information which is received as log-likelihood ratios (LLRs) from soft demodulator at the receiver side. It achieves the adequate bit-error-rate (BER) of $10 -^{6}$ between 2 to 4 dB of bit-energy to noise-power-spectral-density $(\mathrm{E}_{b}/ \mathrm{N}_{0})$ with 10 decoding iterations for various code rates like 1/3, 2/5, 1/2, 2/3, 3/4, 5/6, and 8/9. The VLSI architecture of 5G new-radio LDPC decoder has been field-programmable logic-array (FPGA) prototyped and its implementation results are compared with state-of the-art designs where the proposed LDPC decoder shows lower hardware utilization up to 87%. To the best of our knowledge, this is the first VLSI-architecture of LDPC decoder reported for 5G new-radio compliant to the specifications of enhanced mobile broadband (eMBB).

International Conference on VLSI Design•Jan 1, 2020•19 citations

Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication

Tram Thi Bao Nguyen, Tuy Tan Nguyen, Hanho Lee

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

Electronics•Feb 22, 2021•41 citations

Design and Implementation of Low Bit Error Rate of LDPC Decoder

Ashlesha P. Kshirsagar, Sandeep Kakde, Manish Devendra Chawhan +1 more

Many classes of high-performance Low-density parity check codes are based on parity check matrices composed of permutation sub matrices. The emulation-simulation framework further allows the algorithm and implementation to be iteratively redefined to improve the error floor performance of message passing decoder. Log-Like hood-Ratio (LLR) based Belief-Propagation (BP) algorithm is presented for Low Density Parity Check codes. Numerically accurate representation of check node update computation used in LLR-BP decoding is described. The implementation of Sum-Product algorithm (SPA) within Low Density Parity Check Code (LDPC) decoder is described in this paper and the correction term is used to improve the decoding performance of min-sum algorithm (MSA). Quantization and log-tanh function approximation in sum-product decoder strongly affect which absorbing set dominates in error floor region. For LDPC decoder, bit error rate (BER) decreases with increase in the signal to noise ratio.

International Conference on Communication Systems and Network Technologies•Apr 1, 2015•1 citation
Entering the 5G era, the hardware design of low-density parity-check (LDPC) codes under the new standard has increasingly higher requirements on throughput. According to the geometric characteristics of the check matrices of the quasi-cyclicQC) LDCP codes under the CCSDS standard, this paper designs a layered dynamic normalized minimum sum algorithm(LDNMSA) under the pre-termination decoding based on de-layering scheme. The check matrix structure of this code is easy for hardware design and the storage resource consumption is low. The approximate replacement of the minimum sum algorithm(MSA) reduces the computational complexity of the check node update process. The determination of correction factors and inter-layer deletion thresholds through computer simulation improves the decoding performance and the speed of a single iteration, and adopt the layered scheduling scheme with optimized update order reduces the number of iterations required for decoding. Experimental results show that when the bit error rate(BER) is 10-5, the designed algorithm has a gain of approximately 0.5 dB compared to the MSA. The speed and calculation amounts to a single iteration are much lower than the log-likelihood-ratio(LLR) belief propagation(BP) algorithm and the performance is only less than 0.1dB.
Two methods are proposed to reduce the complexity of the belief propagation (BP) decoding for low-density parity-check (LDPC) codes, with the focus on the layered decoding for quasi-cyclic LDPC (QC-LDPC) codes. The two methods can be separately incorporated into the layered decoding procedures and combined seamlessly to provide the two-fold complexity reduction. In the first method, the message updates regarding a subset of variable nodes are omitted. To construct the subset, the most reliable bit-level channels, derived fromM-ary input channels, are identified. Then, we select the variable nodes with initial log-likelihood ratios (LLRs) exceeding a threshold among the ones assigned to the most reliable bit-level channels to form the subset. The threshold is designed and adjusted based on characteristics of the most reliable bit-level channels. Our numerical results demonstrate that the first method significantly reduces the complexity with negligibly impacting the error-correcting performance. In the second method, each layer of base graphs of QC-LDPC codes uses either sum-product algorithm (SPA) or min-sum algorithm (MSA) to update LLRs. A degree-based algorithm is presented to determine the layers employing either SPA or MSA. We compare with two intuitive methods: 1) applying SPA to randomly selected layers and MSA to the remaining layers, and 2) applying SPA to the core layers of 5G NR LDPC codes and MSA to the remaining layers. According to the numerical results, the degree-based algorithm maximally reduces the complexity while maintaining the same performance. To evaluate the joint method, the first method is applied on top of the second method. Further complexity reduction is achieved without degrading the performance of the second method.
Quasi-cyclic low-density parity-check (QC-LDPC) codes are linear block codes with performance close to the Shannon limit. The layered minimum sum (LMS) decoding algorithm speeds up the decoding convergence by layering the check matrix and updating the nodes according to the layers. However, the MS algorithm has the problem of over estimation and affects the decoding performance due to its simplified strategy of MS algorithm updating the message of check nodes. Therefore, this paper proposes a layered minimum sum decoding algorithm based on overestimation. By setting the correction threshold and updating the check nodes by the conditions, the decoding performance is improved. When the code length is 2048 and the bit error rate is , the proposed algorithm can improve the decoding convergence speed by about 25% and obtain a coding gain of about 0.1 dB.
Low-density parity-check (LDPC) codes have attracted tremendous attention for their excellent error-correction performance and inherent fitness for high-parallelism implementation. With great complexity reduction and friendly for hardware implementation, the min-sum (MS) decoding algorithm for LDPC codes gains widespread applications in practical. In the MS decoding algorithm, finding the first two minima among input variable-to-check messages is the most complex part. To further reduce the complexity of the MS decoding algorithm, an efficient single-minimum (single-min) based layered MS decoding for quasi-cyclic LDPC (QC-LDPC) codes is proposed in this paper. It is found that statistically the difference between the first minimum and second minimum increases as the decoding becomes more convergent. Accordingly, in the proposed single-min scheme, the second minimum is approximately derived based on the first minimum and an index indicating the convergence degree. Besides, some other metrics that are easily obtained are used to refine the second minimum. Simulation results show that the proposed method can significantly improve the error-correction performance and lower the average number of iterations, compared with the state-of-the-art single-min based MS decoding algorithms.
This paper presents partially-parallel low-density parity-check (LDPC) decoder architecture for binary-input additive-white Gaussian-noise (BIAWGN) channel in 5G new-radio cellular-communication technology based on layered min-sum decoding algorithm. This architecture exploits the iterative decomposition of check-node and variable-node combined-processing unit which leads to area optimization and lower hardware complexity. The proposed VLSI architecture of LDPC decoder processes quasi-cyclic LDPC encoded information which is received as log-likelihood ratios (LLRs) from soft demodulator at the receiver side. It achieves the adequate bit-error-rate (BER) of 10−610 -^{6}10−6 between 2 to 4 dB of bit-energy to noise-power-spectral-density (Eb/N0)(\mathrm{E}_{b}/ \mathrm{N}_{0})(Eb​/N0​) with 10 decoding iterations for various code rates like 1/3, 2/5, 1/2, 2/3, 3/4, 5/6, and 8/9. The VLSI architecture of 5G new-radio LDPC decoder has been field-programmable logic-array (FPGA) prototyped and its implementation results are compared with state-of the-art designs where the proposed LDPC decoder shows lower hardware utilization up to 87%. To the best of our knowledge, this is the first VLSI-architecture of LDPC decoder reported for 5G new-radio compliant to the specifications of enhanced mobile broadband (eMBB).
This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.
Many classes of high-performance Low-density parity check codes are based on parity check matrices composed of permutation sub matrices. The emulation-simulation framework further allows the algorithm and implementation to be iteratively redefined to improve the error floor performance of message passing decoder. Log-Like hood-Ratio (LLR) based Belief-Propagation (BP) algorithm is presented for Low Density Parity Check codes. Numerically accurate representation of check node update computation used in LLR-BP decoding is described. The implementation of Sum-Product algorithm (SPA) within Low Density Parity Check Code (LDPC) decoder is described in this paper and the correction term is used to improve the decoding performance of min-sum algorithm (MSA). Quantization and log-tanh function approximation in sum-product decoder strongly affect which absorbing set dominates in error floor region. For LDPC decoder, bit error rate (BER) decreases with increase in the signal to noise ratio.