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FFT-SPA based non-binary LDPC decoder for IEEE 802.11n standard

S. Aruna, M. Anbuselvi

Published Apr 1, 2013• 7 citations
Publisher

Abstract

Non-binary LDPC (NB-LDPC) codes has inherent parallelism and excellent error correcting performance. By comparing with other traditional algorithm, FFT-SPA based non-binary LDPC code gives reduced computation complexity with better decoding performance. In this paper, FFT-SPA based NB-LDPC decoding performance is analyzed for the specification of IEEE 802.11n standard. Parity check matrix (PCM) defines the strength of the LDPC codes. By retaining the properties of the PCM structures, in this paper we propose two modified parity check matrices to reduce the computation strength. For various order of Galois Field with different PCM structures, non-binary LDPC codes performances are analyzed.

DOI
10.1109/iccsp.2013.6577118

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Non-binary LDPC (NB-LDPC) codes has inherent parallelism and excellent error correcting performance. By comparing with other traditional algorithm, FFT-SPA based non-binary LDPC code gives reduced computation complexity with better decoding performance. In this paper, FFT-SPA based NB-LDPC decoding performance is analyzed for the specification of IEEE 802.11n standard. Parity check matrix (PCM) defines the strength of the LDPC codes. By retaining the properties of the PCM structures, in this paper we propose two modified parity check matrices to reduce the computation strength. For various order of Galois Field with different PCM structures, non-binary LDPC codes performances are analyzed.
Low Density Parity Check (LDPC) codes have excellent error correcting performance. LDPC codes are one of the block coding techniques and it performs near Shannon limit and recommended for many practical applications. Non-binary LDPC codes extension of binary LDPC in error correcting property especially for short and moderate block length. In many digital communication systems these codes have strong competitors of turbo codes for error control. Low Density Parity Check as it name is suggests that in a parity check matrix (H) consists of very small number of non-zero elements comparing with zero elements. The strength of the LDPC code defines Parity Check Matrix (PCM). LDPC code contains two types of decoding algorithms hard and soft decision algorithm. By comparing with other traditional decoding algorithm FFT based sum product algorithm reduced computation complexity with better decoding performance. In this paper, LDPC codes for FFT based sum product decoding algorithm performances are analysed for various order of Galois Field GF(q) using AWGN channel. Decoding performance measured in terms of symbol error rate which improve with increasing order of Galois field.
In LDPC code, the structure of code's parity check matrix plays the crucial role in code performance. In this paper proposes the preliminary investigation of a designed parity check matrix from Tanner. We modify this technique in to non binary LDPC structure and decoding with FFT-SPA. We take into high code rate application more than 0.8. The result has shown that in bit error rate (BER) compare between non-binary LDPC and binary LDPC. In our results, the performance of non binary LDPC has better than binary LDPC.
Non-binary LDPC code can achieve better error correcting performance than its binary counterpart especially when the code length is short or moderate. A novel Non-Binary LDPC code is presented in this paper to replace the traditional binary standard in 802.11n system. The proposed Parity Check Matrix (PCM) is optimized by eliminating short-girths and low weight code-words. Partially-parallel quasi-cyclic structure is adopted for the encoder and the check matrix is quasi diagonal line structure. Encoding process directly utilizes check matrix rather than generator matrix to generate check sequence. For decoding process, the (Forward Backward Extended Minimum Sum (FB-EMS) algorithm is adopted. The performance of the proposed Non-binary LDPC code over GF(16) shows more than 1dB coding gain at 10^(-6) BER compared to the traditional binary standard with same bit length for 802.11n standard. Encoder structure and decoder algorithm have been also presented. For practical purposes, this Non-binary quasi-cyclic LDPC code with low complexity makes our proposed system very attractive.
Low density parity check (LDPC) code is a kind of linear block code with excellent performance which is proposed by Dr. Gallager. It overcomes the shortcomings of other error correcting codes and it is the nearest channel code from Shannon limit at the present discover. The decoding algorithms of L DPC code can reduce the decoding delay by the parallel decoding structure, so this has caused great concern in many fields. In recent years more and more scholars begin to study LDPC code, this makes the coding and decoding algorithms of LDPC code improved continuously. LDPC code has been widely used in many fields such as optical fiber communication, digital watermarking, underwater communication and deep space communication because of its excellent performance. Non-binary LDPC code has better performance compared with binary LDPC code. In this paper, FFT-BP decoding algorithm of non-binary LDPC code is studied, and on this basis, we proposed an improved FFT-BP algorithm. The improved decoding algorithm can effectively reduce the average iteration number. Finally, we achieved encode and decode algorithm of non-binary LDPC code with FPGA.
It is well known that non-binary LDPC codes outperform the BER performance of binary LDPC codes for the same code length. The superior BER performance of non-binary codes comes at the expense of more complex decoding algorithms that demand higher computational power. In this paper, we propose parallel signal processing algorithms for performing the FFT-SPA and the corresponding decoding of non-binary LDPC codes over GF(q). The constraints imposed by the complex nature of associated subsystems and kernels, in particular the Check Nodes, present computational challenges regarding multicore systems. Experimental results obtained on GPU for a variety of GF(q) show throughputs in the order of 2 Mbps, which is far above from the minimum throughput required, for example, for real-time video applications that can benefit from such error correcting capabilities.
Low-Density Parity Check (LDPC) codes are linear block codes which perform closer to Shannon"s limit.It is defined by the parity check matrix (PCM) which contains only a few ones in comparison to the number of zeros (sparsity).Stochastic based computation is a method to design lowprecision digital circuits.In stochastic computing, probabilities are encoded by random sequences of bits.In this paper, we focus on the design of Relaxed Half Stochastic (RHS) based algorithm for Non-Binary LDPC decoder, with reduced hardware complexity and optimal decoding performance.Here Sum Product Algorithm (SPA) based variable nodes and stochastic based check nodes are integrated.Thereby the convergence speed of the algorithm is improved.The limitation of the complete stochastic decoder is based on the field order and the degree of variable node.This could be overcome by the method of RHS algorithm.The PCM (Parity Check Matrix) which defines the strength of the LDPC codes contains the non-zero elements.Increasing the sparsity of the PCM, helps in reducing the computation complexity.We propose two modifications in the PCM namely, LDM (Lower Diagonal Matrix) and DDM (Doubly Diagonal Matrix).Decoding performance measured in terms of bit error rate shows that non binary LDPC decoder outperforms than binary LDPC decoder.