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Journal of Computational Methods in Sciences and Engineering

Research on encoding and decoding algorithms of non-binary LDPC code and FPGA implementation

Zhongxun Wang, Baojun Liu, Min Zhang, Yang Lou

Published Aug 20, 2019• 1 citation
Publisher

Abstract

Low density parity check (LDPC) code is a kind of linear block code with excellent performance which is proposed by Dr. Gallager. It overcomes the shortcomings of other error correcting codes and it is the nearest channel code from Shannon limit at the present discover. The decoding algorithms of L DPC code can reduce the decoding delay by the parallel decoding structure, so this has caused great concern in many fields. In recent years more and more scholars begin to study LDPC code, this makes the coding and decoding algorithms of LDPC code improved continuously. LDPC code has been widely used in many fields such as optical fiber communication, digital watermarking, underwater communication and deep space communication because of its excellent performance. Non-binary LDPC code has better performance compared with binary LDPC code. In this paper, FFT-BP decoding algorithm of non-binary LDPC code is studied, and on this basis, we proposed an improved FFT-BP algorithm. The improved decoding algorithm can effectively reduce the average iteration number. Finally, we achieved encode and decode algorithm of non-binary LDPC code with FPGA.

DOI
10.3233/jcm-193806

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Low density parity check (LDPC) code is a kind of linear block code with excellent performance which is proposed by Dr. Gallager. It overcomes the shortcomings of other error correcting codes and it is the nearest channel code from Shannon limit at the present discover. The decoding algorithms of L DPC code can reduce the decoding delay by the parallel decoding structure, so this has caused great concern in many fields. In recent years more and more scholars begin to study LDPC code, this makes the coding and decoding algorithms of LDPC code improved continuously. LDPC code has been widely used in many fields such as optical fiber communication, digital watermarking, underwater communication and deep space communication because of its excellent performance. Non-binary LDPC code has better performance compared with binary LDPC code. In this paper, FFT-BP decoding algorithm of non-binary LDPC code is studied, and on this basis, we proposed an improved FFT-BP algorithm. The improved decoding algorithm can effectively reduce the average iteration number. Finally, we achieved encode and decode algorithm of non-binary LDPC code with FPGA.
In this paper, an improved decoding algorithm for Non-binary low density parity check (NB-LDPC) codes with low decoding complexity and suitable for field-programmable gate array (FPGA) implementation is proposed, which is a mixed logarithmic domain FFT-BP decoding algorithm (Mixed Log-FFT-BP) for the problem of high complexity of the existing decoding algorithms for Non-binary LDPC codes. The algorithm combines the traditional Log-BP algorithm with the FFT-BP algorithm, and simplifies the update of the check nodes in the iterative decoding process. A large number of convolution operations are converted into multiplication operations in frequency domain by using FFT transform and IFFT transform. The multiplication of the original FFT-BP algorithm is converted into the addition and look-up table operations in the logarithmic domain. Then, the logarithm of the probability information is directly solved, so that it can be decoded in the logarithmic domain, which saves the computation of the log likelihood ratio, and then reduces the complexity. Simulation results show that under the additive Gauss white noise channel, when the bit error rate is 10-5, compared with BP algorithm, Log-Bp algorithm and FFT-BP algorithm, the performance of Mixed Log-FFT-BP algorithm is not decreased, and all of them remain within the range of 0.1-0.2dB.
This paper is under in-depth investigation due to suspicion of possible plagiarism on a high similarity index Low Density Parity Check Code（LDPC） is a kind of linear block codes based on sparse check matrix. As a kind of channel coding, whose error performance approach Shannon limits, it has better error correction capability, more flexible structure and lower decoding complexity. Currently most of the LDPC code researches are on the premise of the AWGN channel and BSC channel, which mainly in the range of the binary LDPC codes. According to the above problem, this paper analyzes the various decoding performance of non-binary LDPC codes in Rayleigh channel, and realizes a non-binary LDPC decoder in Rayleigh channel through the FPGA design. The paper begins with an overall discussion of issues surrounding the use of non-binary LDPC codes. And then the bit-error-rate (BER) performances of different non-binary LDPC codes decoding algorithm are compared on the independent Rayleigh fading channel. Finally, this decoder design is implemented based on 5CSEMA5F31C6 FPGA (devised by Altera Company) to illustrate the concepts discussed in the paper.
The non-binary Low Density Parity Check (LDPC) codes over Galois Fields GF(q = 2 p ) have evolved from the binary LDPC codes that are today an industry standard for channel coding. The performance of short block length codes is significantly higher for non-binary LDPC, at the cost of increased decoding complexity. The efficient decoder hardware implementation is still a challenging task. Most of the recently proposed hardware realizations are ASIC-oriented as they employ multiplierless computation units. This article concerns a different decoder design approach that is specifically intended for an FPGA implementation. The reformulated mixed-domain FFT-BP decoding algorithm is applied that does not exclude the multiplication units. This allows mapping a part of the algorithm to the multiplier cores embedded in an FPGA. In this article we concentrate on the important issue of the proper selection of the numeric precision employed. We present the partially parallel extension of the mixed-domain decoder that operates for the structured codes. Then we carefully analyze the finite precision effects on the decoding performance. By simulation and synthesis results we show that it is advantageous to segment the decoder dataflow into 3 parts with different precision. The provided results also facilitate the precision selection for maximum performance or for some performance- complexity tradeoff. Index Terms—Error correcting codes, LDPC codes, Non- binary codes, Iterative decoder, Hardware decoder
Low Density Parity Check (LDPC) codes have excellent error correcting performance. LDPC codes are one of the block coding techniques and it performs near Shannon limit and recommended for many practical applications. Non-binary LDPC codes extension of binary LDPC in error correcting property especially for short and moderate block length. In many digital communication systems these codes have strong competitors of turbo codes for error control. Low Density Parity Check as it name is suggests that in a parity check matrix (H) consists of very small number of non-zero elements comparing with zero elements. The strength of the LDPC code defines Parity Check Matrix (PCM). LDPC code contains two types of decoding algorithms hard and soft decision algorithm. By comparing with other traditional decoding algorithm FFT based sum product algorithm reduced computation complexity with better decoding performance. In this paper, LDPC codes for FFT based sum product decoding algorithm performances are analysed for various order of Galois Field GF(q) using AWGN channel. Decoding performance measured in terms of symbol error rate which improve with increasing order of Galois field.
Non-binary LDPC (NB-LDPC) codes has inherent parallelism and excellent error correcting performance. By comparing with other traditional algorithm, FFT-SPA based non-binary LDPC code gives reduced computation complexity with better decoding performance. In this paper, FFT-SPA based NB-LDPC decoding performance is analyzed for the specification of IEEE 802.11n standard. Parity check matrix (PCM) defines the strength of the LDPC codes. By retaining the properties of the PCM structures, in this paper we propose two modified parity check matrices to reduce the computation strength. For various order of Galois Field with different PCM structures, non-binary LDPC codes performances are analyzed.
Non-binary LDPC codes are obtained by generalizing binary LDPC coeds from finite field GF(2) to finite field GF(q).Its elements of parity check matrix are not(0,1),but ensemble(0,1,…,q-1),and its decoding method still employs belief propagation and iterative algorithm.This paper mainly derives the iterative formulas of decoding algorithm for Non-Binary LDPC codes and analyzes an improved algorithm based on FFT.Finally,the predominant performance of FFT decoding algorithm is verified by simulation.