More computational resources (i.e., more physical qubits and qubit connections) on a superconducting quantum processor not only improve the performance but also result in more complex chip architecture with lower yield rate. Optimizing both of them simultaneously is a difficult problem due to their intrinsic trade-off. Inspired by the application-specific design principle, this paper proposes an automatic design flow to generate simplified superconducting quantum processor architecture with negligible performance loss for different quantum programs. Our architecture-design-oriented profiling method identifies program components and patterns critical to both the performance and the yield rate. A follow-up hardware design flow decomposes the complicated design procedure into three subroutines, each of which focuses on different hardware components and cooperates with corresponding profiling results and physical constraints. Experimental results show that our design methodology could outperform IBM's general-purpose design schemes with better Pareto-optimal results.,0
More computational resources (i.e., more physical qubits and qubit connections) on a superconducting quantum processor not only improve the performance but also result in more complex chip architecture with lower yield rate. Optimizing both of them simultaneously is a difficult problem due to their intrinsic trade-off. Inspired by the application-specific design principle, this paper proposes an automatic design flow to generate simplified superconducting quantum processor architecture with negligible performance loss for different quantum programs. Our architecture-design-oriented profiling method identifies program components and patterns critical to both the performance and the yield rate. A follow-up hardware design flow decomposes the complicated design procedure into three subroutines, each of which focuses on different hardware components and cooperates with corresponding profiling results and physical constraints. Experimental results show that our design methodology could outperform IBM's general-purpose design schemes with better Pareto-optimal results.,0
More computational resources (i.e., more physical qubits and qubit connections) on a superconducting quantum processor not only improve the performance but also result in more complex chip architecture with lower yield rate. Optimizing both of them simultaneously is a difficult problem due to their intrinsic trade-off. Inspired by the application-specific design principle, this paper proposes an automatic design flow to generate simplified superconducting quantum processor architecture with negligible performance loss for different quantum programs. Our architecture-design-oriented profiling method identifies program components and patterns critical to both the performance and the yield rate. A follow-up hardware design flow decomposes the complicated design procedure into three subroutines, each of which focuses on different hardware components and cooperates with corresponding profiling results and physical constraints. Experimental results show that our design methodology could outperform IBM's general-purpose design schemes with better Pareto-optimal results.
More physical qubits and qubit connections integrated on a superconducting quantum processor can improve the ability to execute quantum programs, but on the other hand, they might increase the probability of frequency collisions. Considering a performance and frequency collisions trade-off, it is a feasible method to optimize processor architecture aiming at running specific quantum programs. To this end, we propose a method for designing superconducting quantum processor architectures for the purpose of running specific quantum programs. Different from existing methods, our method is mainly based on graph theory to optimize processor architecture design. First, we convert the trade-off problem into the optimization of the distance between two points as well as the maximum degree in the processor architecture graph. Second, we consider the actual physical routing constraints and build a mathematical model for the optimization problem. Finally, we propose an automatic processor architecture design flow based on the mathematical model, which is implemented with an improved genetic algorithm. To show the effectiveness of our method, we selected sixteen quantum programs with different qubit numbers and different functions for comparison. Simulation results show that the architecture schemes of our method outperform IBM’s general-purpose square lattice architecture schemes. Compared to the general-purpose architecture schemes, the architecture schemes of our method have an average performance improvement of 15.61% and a minimum reduction of 21.33% in the probability of frequency collisions. Furthermore, in most of the selected quantum programs, our architecture schemes perform better than the eff-5-freq’s architecture schemes, with an average 6.58% improvement in performance and a minimum 6.45% reduction in the probability of frequency collisions. Therefore, our method can provide superconducting quantum processor architecture design with better performance and lower probability of frequency collisions for quantum programs.
In the field of superconducting quantum computing, chip architecture design is an important research direction. Currently, most chips are designed for general-purpose architectures, and the fixed connection structure is difficult to ensure the flexibility of mapping, adding extra gate operations and affecting the execution efficiency of different quantum programs. To this end, this paper proposes a superconducting quantum chip architecture design method for quantum programs. The method aims at reducing the number of gates after mapping, and generates a chip architecture with higher fitness by combining the two-qubit gate information of quantum programs through an improved genetic algorithm. The experimental results show that the chip architecture generated by this method outperforms two 2 * 8 scale square lattice generic architectures in 33 test samples, with an average reduction of 35.3 % and 17.9%in the total number of gates optimized, respectively, which verifies the effectiveness of this method.
Superconducting quantum hardware architectures have been designed by considering the physical constraints of the underlying physics. These general-purpose architectures leave room for customization and optimization that can be exploited with alternative architectures specific to the quantum applications that will be executed on the quantum hardware. However, the corresponding design steps are hardly integrated yet and still heavily relies on manual labor. In this work, we provide an initial software framework that aims at providing a foundation to address this drawback. To this end, we first review the design of superconducting quantum hardware architectures and, afterwards, propose a cohesive framework encapsulating the design flow of an application-specific quantum hardware architecture. The resulting framework integrates high-level architecture generation optimized for a quantum application, the physical layout of the architecture, as well as optimization of the layout in a methodical manner. The framework with a reference implementation is available as part of the Munich Quantum Toolkit (MQT) at https://github.com/cda-tum/dasqa under an open-source license.
Abstract Superconducting coupler architecture demonstrates great potential for scalable and high-performance quantum processors, yet how to design efficiently and automatically ‘Qubit–Coupler–Qubit (QCQ)’ of high performance from the layout perspective remains obscure. In this work, this issue is studied for the first time resulting in three key findings. Firstly, we acquire the crucial zero-coupling condition that is only dependent on the geometric design of the layout. Secondly, the upper bound of the qubit–qubit effective coupling is found as 0.0822 ω l / β s 2 which surprisingly depends only on the artificially pre-decided quantities ω l , β s instead of specific layouts. Thirdly, we propose an optimal layout design procedure to reach the very upper bound, leading to efficient and high-performance layout design. The effectiveness of the procedure has been demonstrated scrupulously using electromagnetic simulation experiments. As a stirring application, we report a state-of-the-art 3202 um long-range and scalable QCQ layout that is especially crucial to quantum error correction. Our work provides practical guides to optimize the performance of the existing coupler architecture, find out novel layouts, and further advance the progress of quantum chip design automation.
Quantum computing is a revolutionary approach to computation that leverages the principles of quantum mechanics, enabling computers to process information in fundamentally different ways than classical computers. Unlike traditional bits, which represent data as either 0s or 1s, quantum bits, or qubits, can exist in multiple states simultaneously due to superposition. Additionally, qubits can be entangled, allowing them to be interconnected in ways that enhance computational power and efficiency. This unique behavior has the potential to run certain types of computation tasks much faster than classical computers can, marking a significant leap forward in technology. When building actual quantum computers to run practical quantum algorithms, one needs efficient ways to map the algorithms to the hardware components, similar to compiling classical algorithms onto CPU/GPU hardware. This thesis aims to tackle some of the important problems in the mapping process. First, can we address hardware errors and algorithm errors at the same time? Second, can we build a better circuit complexity metric to inspire better quantum architecture design, and can we design better quantum algorithms and compilation techniques using this improved metric? Lastly, can we use physics-level simulation results to inspire better circuit-level optimization techniques? We hope to provide positive answers to all three questions above through three separate architectural innovations.