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International Symposium on Computer Technology and Information Science (ISCTIS)

A Superconducting Quantum Chip Architecture Design Method for Quantum Programs

Liang Chen, Zhenyu Li, Mengfan Zhang, Lin Han

Published Jul 7, 2023• 3 citations
Publisher

Abstract

In the field of superconducting quantum computing, chip architecture design is an important research direction. Currently, most chips are designed for general-purpose architectures, and the fixed connection structure is difficult to ensure the flexibility of mapping, adding extra gate operations and affecting the execution efficiency of different quantum programs. To this end, this paper proposes a superconducting quantum chip architecture design method for quantum programs. The method aims at reducing the number of gates after mapping, and generates a chip architecture with higher fitness by combining the two-qubit gate information of quantum programs through an improved genetic algorithm. The experimental results show that the chip architecture generated by this method outperforms two 2 * 8 scale square lattice generic architectures in 33 test samples, with an average reduction of 35.3 % and 17.9%in the total number of gates optimized, respectively, which verifies the effectiveness of this method.

DOI
10.1109/isctis58954.2023.10213168

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In the field of superconducting quantum computing, chip architecture design is an important research direction. Currently, most chips are designed for general-purpose architectures, and the fixed connection structure is difficult to ensure the flexibility of mapping, adding extra gate operations and affecting the execution efficiency of different quantum programs. To this end, this paper proposes a superconducting quantum chip architecture design method for quantum programs. The method aims at reducing the number of gates after mapping, and generates a chip architecture with higher fitness by combining the two-qubit gate information of quantum programs through an improved genetic algorithm. The experimental results show that the chip architecture generated by this method outperforms two 2 * 8 scale square lattice generic architectures in 33 test samples, with an average reduction of 35.3 % and 17.9%in the total number of gates optimized, respectively, which verifies the effectiveness of this method.
More physical qubits and qubit connections integrated on a superconducting quantum processor can improve the ability to execute quantum programs, but on the other hand, they might increase the probability of frequency collisions. Considering a performance and frequency collisions trade-off, it is a feasible method to optimize processor architecture aiming at running specific quantum programs. To this end, we propose a method for designing superconducting quantum processor architectures for the purpose of running specific quantum programs. Different from existing methods, our method is mainly based on graph theory to optimize processor architecture design. First, we convert the trade-off problem into the optimization of the distance between two points as well as the maximum degree in the processor architecture graph. Second, we consider the actual physical routing constraints and build a mathematical model for the optimization problem. Finally, we propose an automatic processor architecture design flow based on the mathematical model, which is implemented with an improved genetic algorithm. To show the effectiveness of our method, we selected sixteen quantum programs with different qubit numbers and different functions for comparison. Simulation results show that the architecture schemes of our method outperform IBM’s general-purpose square lattice architecture schemes. Compared to the general-purpose architecture schemes, the architecture schemes of our method have an average performance improvement of 15.61% and a minimum reduction of 21.33% in the probability of frequency collisions. Furthermore, in most of the selected quantum programs, our architecture schemes perform better than the eff-5-freq’s architecture schemes, with an average 6.58% improvement in performance and a minimum 6.45% reduction in the probability of frequency collisions. Therefore, our method can provide superconducting quantum processor architecture design with better performance and lower probability of frequency collisions for quantum programs.
More computational resources (i.e., more physical qubits and qubit connections) on a superconducting quantum processor not only improve the performance but also result in more complex chip architecture with lower yield rate. Optimizing both of them simultaneously is a difficult problem due to their intrinsic trade-off. Inspired by the application-specific design principle, this paper proposes an automatic design flow to generate simplified superconducting quantum processor architecture with negligible performance loss for different quantum programs. Our architecture-design-oriented profiling method identifies program components and patterns critical to both the performance and the yield rate. A follow-up hardware design flow decomposes the complicated design procedure into three subroutines, each of which focuses on different hardware components and cooperates with corresponding profiling results and physical constraints. Experimental results show that our design methodology could outperform IBM's general-purpose design schemes with better Pareto-optimal results.
More computational resources (i.e., more physical qubits and qubit connections) on a superconducting quantum processor not only improve the performance but also result in more complex chip architecture with lower yield rate. Optimizing both of them simultaneously is a difficult problem due to their intrinsic trade-off. Inspired by the application-specific design principle, this paper proposes an automatic design flow to generate simplified superconducting quantum processor architecture with negligible performance loss for different quantum programs. Our architecture-design-oriented profiling method identifies program components and patterns critical to both the performance and the yield rate. A follow-up hardware design flow decomposes the complicated design procedure into three subroutines, each of which focuses on different hardware components and cooperates with corresponding profiling results and physical constraints. Experimental results show that our design methodology could outperform IBM's general-purpose design schemes with better Pareto-optimal results.,0
Full connectivity of qubits is necessary for most quantum algorithms, which is difficult to directly implement on Noisy Intermediate-Scale Quantum processors. However, inserting swap gate to enable the two-qubit gates between uncoupled qubits significantly decreases the computation result fidelity. To this end, we propose a Special-Purpose Quantum Processor Design method that can design suitable structures for different quantum algorithms. Our method extends the processor structure from two-dimensional lattice graph to general planar graph and arranges the physical couplers according to the two-qubit gate distribution between the logical qubits of the quantum algorithm and the physical constraints. Experimental results show that our design methodology, compared with other methods, could reduce the number of extra swap gates per two-qubit gate by at least 104.2% on average. Also, our method's advantage over other methods becomes more obvious as the depth and qubit number increase. The result reveals that our method is competitive in improving computation result fidelity and it has the potential to demonstrate quantum advantage under the technical conditions.
Routing design is an important aspect in aiding the completion of the Quantum Processing Unit (QPU) layout design for large-scale superconducting quantum processors. One of the research focuses is how to generate reliable routing schemes within a short time. In this study, we propose a superconducting quantum processor auto-routing method for supporting scalable architecture, which is mainly implemented through the bidirectional A star algorithm, the backtracking algorithm, and the greedy strategy. By using this method, the number of crossovers and corners can be reduced while efficiently completing the processor routing. To verify the effectiveness of our method, we selected 5 types of qubit numbers for processor routing experiments. The experimental results show that compared to the improved A star algorithm of Qiskit Metal, our method reduces the average execution time by at least 43.61% and 41.68% in serial and parallel, respectively. Compared with four other routing algorithms, our method has a minimum average reduction of 10.63% and 1.21% in the number of crossovers and corners, respectively. In addition, our method supports the processor routing design of planar and flip-chip architectures, and can automatically process both airbridge and insulation types of crossovers. Therefore, our method can provide efficient and reliable automated routing design to assist the development of large-scale superconducting quantum processors.
Recently, the development of quantum chips has made great progress-- the number of qubits is increasing and the fidelity is getting higher. However, qubits of these chips are not always fully connected, which sets additional barriers for implementing quantum algorithms and programming quantum programs. In this paper, we introduce a general circuit optimizing scheme, which can efficiently adjust and optimize quantum circuits according to arbitrary given qubits' layout by adding additional quantum gates, exchanging qubits and merging single-qubit gates. Compared with the optimizing algorithm of IBM's QISKit, the quantum gates consumed by our scheme is 74.7%, and the execution time is only 12.9% on average.