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arXiv:2305.07052 · IEEE International Symposium on Multiple-Valued Logic (ISMVL)

A Framework for the Design and Realization of Alternative Superconducting Quantum Architectures

Jagatheesan Kunasaikaran, Kevin Mato, Robert Wille

Published May 28, 2024• 3 citations
arXivHTMLPDF

Abstract

Superconducting quantum hardware architectures have been designed by considering the physical constraints of the underlying physics. These general-purpose architectures leave room for customization and optimization that can be exploited with alternative architectures specific to the quantum applications that will be executed on the quantum hardware. However, the corresponding design steps are hardly integrated yet and still heavily relies on manual labor. In this work, we provide an initial software framework that aims at providing a foundation to address this drawback. To this end, we first review the design of superconducting quantum hardware architectures and, afterwards, propose a cohesive framework encapsulating the design flow of an application-specific quantum hardware architecture. The resulting framework integrates high-level architecture generation optimized for a quantum application, the physical layout of the architecture, as well as optimization of the layout in a methodical manner. The framework with a reference implementation is available as part of the Munich Quantum Toolkit (MQT) at https://github.com/cda-tum/dasqa under an open-source license.

DOI
10.1109/ismvl60454.2024.00027

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Superconducting quantum hardware architectures have been designed by considering the physical constraints of the underlying physics. These general-purpose architectures leave room for customization and optimization that can be exploited with alternative architectures specific to the quantum applications that will be executed on the quantum hardware. However, the corresponding design steps are hardly integrated yet and still heavily relies on manual labor. In this work, we provide an initial software framework that aims at providing a foundation to address this drawback. To this end, we first review the design of superconducting quantum hardware architectures and, afterwards, propose a cohesive framework encapsulating the design flow of an application-specific quantum hardware architecture. The resulting framework integrates high-level architecture generation optimized for a quantum application, the physical layout of the architecture, as well as optimization of the layout in a methodical manner. The framework with a reference implementation is available as part of the Munich Quantum Toolkit (MQT) at https://github.com/cda-tum/dasqa under an open-source license.
Quantum computing is fast evolving as a technology due to recent advances in hardware, software, as well as the development of promising applications. To use this technology for solving specific problems, a suitable quantum algorithm has to be determined, the problem has to be encoded in a form suitable for the chosen algorithm, it has to be executed, and the result has to be decoded. To date, each of these tedious and error-prone steps is conducted in a mostly manual fashion. This creates a high entry barrier for using quantum computing—especially for users with little to no expertise in that domain. In this work, we envision a framework that aims to lower this entry barrier by allowing users to employ quantum computing solutions in an automatic fashion. To this end, interfaces as similar as possible to classical solvers are provided, while the quantum steps of the workflow are shielded from the user as much as possible by a fully automated backend. To demonstrate the feasibility and usability of such a framework, we provide proof-of-concept implementations for two different classes of problems which are publicly available on GitHub (https://github.com/cda-tum/MQTProblemSolver) as part of the Munich Quantum Toolkit (MQT). By this, this work provides the foundation for a low-threshold approach realizing quantum computing solutions with no or only moderate expertise in this technology.
Quantum software tools for a wide variety of design tasks on and across different levels of abstraction are crucial in order to eventually realize useful quantum applications. This requires practical and relevant benchmarks for new software tools to be empirically evaluated and compared to the current state of the art. Although benchmarks for specific design tasks are commonly available, the demand for an overarching cross-level benchmark suite has not yet been fully met and there is no mutual consolidation in how quantum software tools are evaluated thus far. In this work, we propose the MQT Bench benchmark suite (as part of the Munich Quantum Toolkit , MQT) based on four core traits: (1) cross-level support for different abstraction levels, (2) accessibility via an easy-to-use web interface (https://www.cda.cit.tum.de/mqtbench/) and a Python package, (3) provision of a broad selection of benchmarks to facilitate generalizability, as well as (4) extendability to future algorithms, gate-sets, and hardware architectures. By comprising more than 70,000 benchmark circuits ranging from 2 to 130 qubits on four abstraction levels, MQT Bench presents a first step towards benchmarking different abstraction levels with a single benchmark suite to increase comparability, reproducibility, and transparency.
More computational resources (i.e., more physical qubits and qubit connections) on a superconducting quantum processor not only improve the performance but also result in more complex chip architecture with lower yield rate. Optimizing both of them simultaneously is a difficult problem due to their intrinsic trade-off. Inspired by the application-specific design principle, this paper proposes an automatic design flow to generate simplified superconducting quantum processor architecture with negligible performance loss for different quantum programs. Our architecture-design-oriented profiling method identifies program components and patterns critical to both the performance and the yield rate. A follow-up hardware design flow decomposes the complicated design procedure into three subroutines, each of which focuses on different hardware components and cooperates with corresponding profiling results and physical constraints. Experimental results show that our design methodology could outperform IBM's general-purpose design schemes with better Pareto-optimal results.
As the capabilities of quantum computing hardware continue to rise, algorithms that exploit them are becoming increasingly complex. These developments increase the need for sophisticated compilation frameworks that translate high-level algorithms into executable code. In the past, most solutions were built with a quantum-first approach and handled mostly pure quantum programs without classical elements such as structured control flow. However, developments in quantum algorithms, error correction, and optimization, as well as the integration into high-performance computing (HPC) environments, depend on such classical elements. As quantum-first approaches increasingly struggle to handle these concepts, classical-first approaches are becoming a promising alternative. In this work, we present the MQT Compiler Collection, a blueprint for a future-proof quantum-classical compilation framework built on the Multi-Level Intermediate Representation (MLIR). After years of experience with the quantum-first approach and its shortcomings, we propose a framework that embraces core MLIR concepts to support the full compilation pipeline from high-level algorithms to hardware-specific instructions. The proposed architecture is designed from the ground up to support complex optimizations beyond, e.g., simple gate cancellation. It is publicly available at https://github.com/munich-quantum-toolkit/core.
Recent advancements in quantum computing software are gradually increasing the scope and size of quantum programs being developed. At the same time, however, these larger programs provide more possibilities for functional errors that are harder to detect and resolve. Meanwhile, debugging tools that could aid developers in resolving these errors are still barely existent and far from what we take for granted in classical design automation and software engineering. As a result, even if one manages to identify the incorrect behavior of a developed quantum program, detecting and resolving the underlying errors in the program remains a time-consuming and tedious task. Moreover, the exponential growth of the state space in quantum programs makes the efficient manual investigation of errors radically difficult even for respectively simple algorithms, and almost impossible as the number of qubits increases. To address this problem, this work proposes a debugging framework, available as an open-source implementation at https://github.com/cda-tum/mqt-debugger. It assists developers in debugging errors in quantum programs, allowing them to efficiently identify the existence of errors and diagnose their causes. Users are given the ability to place assertions in the code that test for the correctness of a given algorithm and are evaluated using classical simulations of the underlying quantum program. Once an assertion fails, the proposed framework employs different diagnostic methods to point towards possible error causes. This way, the debugging workload for quantum programs is drastically reduced.
More computational resources (i.e., more physical qubits and qubit connections) on a superconducting quantum processor not only improve the performance but also result in more complex chip architecture with lower yield rate. Optimizing both of them simultaneously is a difficult problem due to their intrinsic trade-off. Inspired by the application-specific design principle, this paper proposes an automatic design flow to generate simplified superconducting quantum processor architecture with negligible performance loss for different quantum programs. Our architecture-design-oriented profiling method identifies program components and patterns critical to both the performance and the yield rate. A follow-up hardware design flow decomposes the complicated design procedure into three subroutines, each of which focuses on different hardware components and cooperates with corresponding profiling results and physical constraints. Experimental results show that our design methodology could outperform IBM's general-purpose design schemes with better Pareto-optimal results.,0