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IEEE International Superconductive Electronics Conference (ISEC)

Fast RSFQ and ERSFQ Parallel Counters

M. Celik, Timur V. Filippov, Anubhav Sahu, Dmitri E. Kirichenko, Saad M. Sarwana, A. Erik Lehmann, Deepnarayan Gupta

Published Jul 1, 2019• 2 citations
Publisher

Abstract

Historically one of the most challenging high-speed RSFQ circuits to implement has been a parallel counter that sums a set of unweighted inputs and produces a binary-weighted word at the same clock rate. A 7-to-3 parallel counter that sums 7 inputs has been designed and tested at clock frequencies up to 50 GHz using its own dedicated testbed. Yielded in both 10- and 20-kA/cm2 current densities using MIT Lincoln Laboratory's foundry, this 7-to-3 summing circuit has become a digital circuit benchmark. Most recently, a version with 15 parallel inputs producing a 4-bit output was designed using two flavors of 8-to-4 summing circuits. The first (8-to-4a), based on the 7-to-3 parallel counter, sums 8 unweighted inputs whereas the second (8-to-4b) sums two 4-bit binary-weighted words by pairwise summing of bits of equal weights from two 8-to-4a blocks. Design considerations for scaling this circuit will be discussed together with the circuit performance and yield.

DOI
10.1109/isec46533.2019.8990923

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Historically one of the most challenging high-speed RSFQ circuits to implement has been a parallel counter that sums a set of unweighted inputs and produces a binary-weighted word at the same clock rate. A 7-to-3 parallel counter that sums 7 inputs has been designed and tested at clock frequencies up to 50 GHz using its own dedicated testbed. Yielded in both 10- and 20-kA/cm2 current densities using MIT Lincoln Laboratory's foundry, this 7-to-3 summing circuit has become a digital circuit benchmark. Most recently, a version with 15 parallel inputs producing a 4-bit output was designed using two flavors of 8-to-4 summing circuits. The first (8-to-4a), based on the 7-to-3 parallel counter, sums 8 unweighted inputs whereas the second (8-to-4b) sums two 4-bit binary-weighted words by pairwise summing of bits of equal weights from two 8-to-4a blocks. Design considerations for scaling this circuit will be discussed together with the circuit performance and yield.
Historically one of the most challenging high-speed rapid single flux quantum circuits to implement has been a parallel counter that sums a set of unweighted inputs and produces a binary-weighted word at the same clock rate. A 7-to-3 parallel counter that sums seven inputs has been designed and tested at the target clock frequency of 40 GHz and at frequencies up to 50 GHz using its own dedicated testbed. Yielded in both 10- and 20-kA/cm2 current densities using MIT Lincoln Laboratory's foundry, this 7-to-3 summing circuit has become a digital circuit benchmark. Most recently, a version with 15 parallel inputs producing a 4-bit output at the same target frequency was designed by combining 2 variants of 8-to-4 parallel counters. The first variant based on the 7-to-3 parallel counter, sums eight unweighted inputs, whereas the second variant sums two 4-bit binary-weighted words by pairwise summing of bits of equal weights. Design considerations for scaling this circuit will be discussed together with the circuit performance and yield.
We have designed and demonstrated two versions of an ERSFQ 8-bit parallel adder. ERSFQ is a resistor-free approach to dc biasing of Single Flux Quantum circuits that dissipates orders of magnitude less power than a traditional RSFQ logic while operating and has zero dissipation in inactive mode. The adders were designed for and fabricated with various fabrication processes, including HYPRES's 1.0-μm 4-layer 4.5 kA/cm2process, HYPRES's 0.25-μm 4-layer 4.5 kA/cm2process, HYPRES's 0.25-μm 6-layer 4.5 kA/cm2planarized process, and MIT Lincoln Lab's 0.25-μm 4-layer 10 kA/cm2process. These circuits serve as a good LSI fabrication process benchmark. We describe design and report on test results of all versions of the adder.
We have designed and RSFQ multiplier-accumulator, the central component of our decimation digital filter. The circuit consists of 38 synchronous RSFQ cells of six types arranged into a rectangular systolic array fed by one parallel input and one serial input. Timing is based on counter-flow clock distribution scheme with simulated maximum clock frequency of 11 GHz. The circuit, fabricated at Hypres, Inc., contains 1100 Josephson junctions, has power consumption less than 0.2 mW, and area less than 2.5 mm/sup 2/. The multiplier-accumulator has been tested at low frequency demonstrating full functionality and stable operation over a 24 hour testing period. This four-bit multiplier accumulator is one of the largest reported RSFQ circuits verified experimentally to date.
We have designed and tested a parallel 8-bit ERSFQ binary shifter that is one of the essential circuits in the design of the energy-efficient superconducting CPU. The binary shifter performs a bidirectional SHIFT instruction of an 8-bit argument. It consists of a bidirectional triple-port shift register controlled by two (left and right) shift pulse generators asynchronously generating a set number of shift pulses. At first clock cycle, an 8-bit word is loaded into the binary shifter and a 3-bit shift argument is loaded into the desired shift-pulse generator. Next, the generator produces the required number of shift SFQ pulses (from 0 to 7) asynchronously, with a repetition rate set by the internal generator delay of ~ 30 ps. These SFQ pulses are applied to the left (positive) or the right (negative) input of the binary shifter. Finally, after the shift operation is completed, the resulting 8-bit word goes to the parallel output. The complete 8-bit ERSFQ binary shifter, consisting of 820 Josephson junctions, was simulated and optimized using PSCAN2. It was fabricated in MIT Lincoln Lab's 10-kA/cm2SFQ5ee fabrication process with a high-kinetic inductance layer. We have successfully tested the binary shifter at both the LSB-to-MSB and MSB-to-LSB propagation regimes for all eight shift arguments. A single shift operation on a single input word demonstrated operational margins of ±16% of the dc bias current. The correct functionality of the 8-bit ERSFQ binary shifter with the large, exhaustive data pattern was observed within ±10% margins of the dc bias current. In this paper, we describe the design and present the test results for the ERSFQ 8-bit parallel binary shifter.
We have developed an advanced version of on-chip test system with new high-speed clock generation and control. For high-speed clock generation, a novel wide-bandwidth ring generator is designed using circular Josephson transmission lines with an inductively coupled trigger. The generator is capable of producing SFQ clock pulses in the range of from 15 to 55 GHz using a 1 kA/cm/sup 2/ Nb fabrication process. For clock control, we have designed two different types of clock-controller circuits based on programmable shift-register and counter. Using the on-chip test system, we have successfully tested a parallel multiplier module up to 15 GHz with 16% dc bias margins.
We have designed and tested a parallel 8-bit ERSFQ arithmetic logic unit (ALU). The ALU design employs wave-pipelined instruction execution and features modular bit-slice architecture that is easily extendable to any number of bits and adaptable to current recycling. A carry signal synchronized with an asynchronous instruction propagation provides the wave-pipeline operation of the ALU. The ALU instruction set consists of 14 arithmetical and logical instructions. It has been designed and simulated for operation up to a 10 GHz clock rate at the 10-kA/cm2fabrication process. The ALU is embedded into a shift-register-based high-frequency testbed with on-chip clock generator to allow for comprehensive high frequency testing for all possible operands. The 8-bit ERSFQ ALU, comprising 6840 Josephson junctions, has been fabricated with MIT Lincoln Lab's 10-kA/cm2SFQ5ee fabrication process featuring eight Nb wiring layers and a high-kinetic inductance layer needed for ERSFQ technology. We evaluated the bias margins for all instructions and various operands at both low and high frequency clock. At low frequency, clock and all instruction propagation through ALU were observed with bias margins of +/-11% and +/-9%, respectively. Also at low speed, the ALU exhibited correct functionality for all arithmetical and logical instructions with +/-6% bias margins. We tested the 8-bit ALU for all instructions up to 2.8 GHz clock frequency.