We have developed an advanced version of on-chip test system with new high-speed clock generation and control. For high-speed clock generation, a novel wide-bandwidth ring generator is designed using circular Josephson transmission lines with an inductively coupled trigger. The generator is capable of producing SFQ clock pulses in the range of from 15 to 55 GHz using a 1 kA/cm/sup 2/ Nb fabrication process. For clock control, we have designed two different types of clock-controller circuits based on programmable shift-register and counter. Using the on-chip test system, we have successfully tested a parallel multiplier module up to 15 GHz with 16% dc bias margins.
We have developed an advanced version of on-chip test system with new high-speed clock generation and control. For high-speed clock generation, a novel wide-bandwidth ring generator is designed using circular Josephson transmission lines with an inductively coupled trigger. The generator is capable of producing SFQ clock pulses in the range of from 15 to 55 GHz using a 1 kA/cm/sup 2/ Nb fabrication process. For clock control, we have designed two different types of clock-controller circuits based on programmable shift-register and counter. Using the on-chip test system, we have successfully tested a parallel multiplier module up to 15 GHz with 16% dc bias margins.
We have experimentally demonstrated high-speed operation of RSFQ circuits using on-chip testing system and confirmed normal operation up to 30 GHz. The system includes high-frequency pulse generators and shift registers (SRs) serving as an interface circuit between high-speed internal signals and low-speed external signals. We adopted two ladder-type pulse generators. One generates clock pulses of 10 GHz and the other generates 25 GHz. By increasing bias currents of JTLs, clock pulses can be generated at higher frequency. By using the system, an SR and a T flip-flop (TFF) gate are examined. The circuits were fabricated by NEC's standard process based on Nb/AlO x /Nb junction technology with J c = 2.5 kA cm -2 . We optimized circuit parameters by using Monte Carlo simulation. In addition, the effect of parasitic inductances can be reduced by decreasing I c . As a result, the systems for SR and TFF worked correctly up to 30 GHz and 27.5 GHz, respectively. The SR and TFF have wide bias margins of ±39% and ±20%, respectively. We confirmed that the bias margins of the SR are independent of operation frequency. The limits of operation frequency are thought to be much higher than 30 GHz.
Experimental superconducting shift registers con- sisting of on-chip clock generators, clock regeneration and dis- tribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic / memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed opera- tion of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AIO,/Nb Josephson-junction process at a critical-current density of 1000 A / cm2. The power dissipation per bit is 3 p.W.
Experimental superconducting shift registers consisting of on-chip clock generators, clock regeneration and distribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic/memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed operation of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AlO/sub /x/Nb Josephson-junction process at a critical-current density of 1000 A/cm/sup 2/. The power dissipation per bit is 3 mu W.>
An eight-bit SFQ processor has been designed and some key components have been tested to confirm feasibility of the large-scale SFQ digital circuit. The designed processor is composed of a one-bit ALU, two eight-bit registers with local clock generators, an instruction register, a five-bit program counter, a state controller, and a 32-byte register file. A bit-serial architecture and a distributed local clock architecture, where each register has its own local clock generator, have been employed in order to increase the local clock frequency. The target clock frequency is 16 GHz and 10 GHz for the NEC 2.5 kA/cm/sup 2/ and Hypres 1 kA/cm/sup 2/ Nb processes. On the circuit design level, we have used a data-driven self-timed architecture and a binary decision diagram, which reduce the timing design difficulty in high frequency operation. The processor, which contains 7,300 Josephson junctions, has been designed by using a cell-based design methodology with the assistance of a top-down CAD environment. We have successfully tested some important circuit blocks, including a one-bit ALU, eight-bit registers, and a demultiplexer for register files.
Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.
Superconducting single flux quantum (SFQ) circuits can process information at extremely high speeds, in the range of hundreds of GHz. SFQ circuits are based on Josephson junction cells for switching logic and ballistic transmission for transferring SFQ pulses. Multi-chip modules (MCMs) are often used to implement larger complex designs, which cannot be fit onto a single chip. We have optimized the design of wideband interconnects for transferring signals and SFQ pulses between chips in flip-chip MCMs and evaluated the importance of several design parameters such as the geometry of bump pads on chips, length of passive microstrip lines (MSLs) and number of corners in MSLs as well as flux trapping and fabrication effects on the operating margins of the MCMs. Several test circuits have been designed to evaluate the above mentioned features and fabricated in the framework of a 4.5 kA cm −2 HYPRES process. The MCM bumps for electrical connections have been deposited using a wafer-level electroplating process. We have found that, at the optimized configuration, the maximum operating frequency of the MCM test circuit, a ring oscillator with chip-to-chip connections, approaches 100 GHz and is not noticeably affected by the presence of MCM interconnects, decreasing by only about 3% with respect to the same circuit with no inter-chip connections.