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IEEE Transactions on Applied Superconductivity

Bit-Slice Butterfly Processing Units for 64-Point RSFQ FFT Processors

Guang-Ming Tang, Pei-Yao Qu, Xiangyu Zheng, Jia-Hong Yang, Xiaochun Ye, Dongrui Fan, Ninghui Sun

Published Jul 30, 2019• 10 citations
Publisher

Abstract

In this article, 8-bit bit-slice butterfly processing units (BPUs) are proposed for 64-point rapid single-flux-quantum (RSFQ) fast Fourier transform processors. The BPUs are based on radix-2, mixed-radix, and split-radix algorithms, respectively. Unlike the previously developed bit-serial RSFQ BPUs, the proposed bit-slice BPUs continuously process 64-point data divided into eight slices of eight points each in order to reduce the hardware cost. The BPUs use synchronous concurrent-flow clocking and they can be extended to any n2-point processing.

DOI
10.1109/tasc.2019.2931893

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In this article, 8-bit bit-slice butterfly processing units (BPUs) are proposed for 64-point rapid single-flux-quantum (RSFQ) fast Fourier transform processors. The BPUs are based on radix-2, mixed-radix, and split-radix algorithms, respectively. Unlike the previously developed bit-serial RSFQ BPUs, the proposed bit-slice BPUs continuously process 64-point data divided into eight slices of eight points each in order to reduce the hardware cost. The BPUs use synchronous concurrent-flow clocking and they can be extended to any n2-point processing.
We have designed a Decimation-in-Time (DIT) radix 2 butterfly integrated circuit. This circuit will be used to implement the 32-point Fast Fourier Transform (FFT) in a parallel data flow architecture. The radix 2 butterfly circuit uses serial RSFQ math and consists of four single bit-wide serial multipliers and eight carry-save serial adders. The circuit with 16-bit word-length employs only 3400 junctions, occupies an area of 3.8/spl times/2.0 mm/sup 2/, and dissipates less than 1.1 mW power. The multiplier is implemented using the unique RSFQ bit-clock-pipelined schema. We have successfully tested a library of serial multiply-add elements: the 8-bit multiplier at 6.3 GHz and adders with dc bias margin /spl plusmn/20%. Finally, we have demonstrated full operation of the radix 2 butterfly chip with 5-bit word length.>
The Fast Fourier Transform (FFT) is extensively used in image processing, wireless communication, and other applications. Some applications that involve very complicated, real-time FFT processing require specialized hardware for performing high-speed FFT processing. We have been developing high-speed FFT processors based on single flux quantum (SFQ) circuit technology. In this study, we developed a butterfly processing element for FFT processors that uses SFQ circuits. The butterfly processing element consists of complex number adders, subtractors, and multipliers. The circuit structure was modified compared to that of previous SFQ FFT processors to reduce latency. Several buffer circuits were inserted in the multipliers to compensate for timing jitter accumulation and discrepancies due to signal propagation delay. We designed and implemented a four-bit bit-serial butterfly processing element that contains 5763 Josephson junctions using the ISTEC Nb 2.5-kA/cm2standard 2 process and the CONNECT cell library. Correct operation of the butterfly processing unit was experimentally confirmed at a clock frequency of 25 GHz.
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In this paper we present an FFT hardware accelerator based on a butterfly (BUT) structure implemented in Rapid Single-Flux-Quantum (RSFQ) superconducting computing. Our design uses a data representation that combines Race Logic (RL) with pulse streams in order to perform arithmetic operations and generate twiddle factors efficiently. Given today’s stringent area limitations for RSFQ technology, our design aims to maximize area efficiency. Our design shows 2 to 18× higher throughput per area, measured as performance per number of Josephson junctions. Moreover, we demonstrate 20-70% area savings compared to binary RSFQ FFT implementations for 2 to 64 N-points.
A 4-bit bit-slice multiplier for a 32-bit rapid single-flux-quantum (RSFQ) microprocessor is proposed. It carries out both signed and unsigned integer multiplication. A fully pipelined RSFQ logic design of the multiplier using concurrent flow clocking consists of 33 stages and 17,551 Josephson junctions. The bit-slice approach simplifies the circuit complexity and reduces the hardware cost. For verification, an 8×8-bit 4-bit bit-slice multiplier based on the proposed algorithm has been designed and simulated using AIST 10-kA/cm21.0-μm fabrication technology. The simulation result shows correct operation at 62.5 GHz.
We have been working on the development of a high-speed fast Fourier transform (FFT) processor using single-flux-quantum (SFQ) logic circuits. In our previous studies, we designed and demonstrated a 4-bit butterfly processor, a data-shuffling circuit, and a twiddle factor ROM for 4-bit 8-point FFT using the AIST 10 kA/cm2Nb advanced process 2 at maximum frequencies of 51.6, 59.5, and 51.5, respectively. In this study, to complete the FFT processor design, we designed and demonstrated residual component circuits called a rounding circuit and a data buffer at a target frequency of 50 GHz. We also designed and experimentally confirmed the operation of an SFQ-based single-chip FFT processor integrating all the component circuits.