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IEEE Transactions on Applied Superconductivity

Implementation of a FFT radix 2 butterfly using serial RSFQ multiplier-adders

Oleg A. Mukhanov, Alex F. Kirichenko

Published Jun 1, 1995• 52 citations
Publisher

Abstract

We have designed a Decimation-in-Time (DIT) radix 2 butterfly integrated circuit. This circuit will be used to implement the 32-point Fast Fourier Transform (FFT) in a parallel data flow architecture. The radix 2 butterfly circuit uses serial RSFQ math and consists of four single bit-wide serial multipliers and eight carry-save serial adders. The circuit with 16-bit word-length employs only 3400 junctions, occupies an area of 3.8/spl times/2.0 mm/sup 2/, and dissipates less than 1.1 mW power. The multiplier is implemented using the unique RSFQ bit-clock-pipelined schema. We have successfully tested a library of serial multiply-add elements: the 8-bit multiplier at 6.3 GHz and adders with dc bias margin /spl plusmn/20%. Finally, we have demonstrated full operation of the radix 2 butterfly chip with 5-bit word length.>

DOI
10.1109/77.403089

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We have designed a Decimation-in-Time (DIT) radix 2 butterfly integrated circuit. This circuit will be used to implement the 32-point Fast Fourier Transform (FFT) in a parallel data flow architecture. The radix 2 butterfly circuit uses serial RSFQ math and consists of four single bit-wide serial multipliers and eight carry-save serial adders. The circuit with 16-bit word-length employs only 3400 junctions, occupies an area of 3.8/spl times/2.0 mm/sup 2/, and dissipates less than 1.1 mW power. The multiplier is implemented using the unique RSFQ bit-clock-pipelined schema. We have successfully tested a library of serial multiply-add elements: the 8-bit multiplier at 6.3 GHz and adders with dc bias margin /spl plusmn/20%. Finally, we have demonstrated full operation of the radix 2 butterfly chip with 5-bit word length.>
The Fast Fourier Transform (FFT) is extensively used in image processing, wireless communication, and other applications. Some applications that involve very complicated, real-time FFT processing require specialized hardware for performing high-speed FFT processing. We have been developing high-speed FFT processors based on single flux quantum (SFQ) circuit technology. In this study, we developed a butterfly processing element for FFT processors that uses SFQ circuits. The butterfly processing element consists of complex number adders, subtractors, and multipliers. The circuit structure was modified compared to that of previous SFQ FFT processors to reduce latency. Several buffer circuits were inserted in the multipliers to compensate for timing jitter accumulation and discrepancies due to signal propagation delay. We designed and implemented a four-bit bit-serial butterfly processing element that contains 5763 Josephson junctions using the ISTEC Nb 2.5-kA/cm2standard 2 process and the CONNECT cell library. Correct operation of the butterfly processing unit was experimentally confirmed at a clock frequency of 25 GHz.
Abstract: We have developed and experimentally evaluated at high-speed, a complete set of arithmetic circuits (multiply, add, and accumulate) for high performance digital signal processing (DSP). These circuits take advantage of the unique features of the Rapid Single-Flux Quantum (RSFQ) logic/memory family, including fusion of logic and memory functions at the gate level, pulse representation of clock and data, and the ability to maintain inter cell propagation delays using Josephson transmission lines (JTLs). The circuits developed have been successfully used in the implementation of a serial radix 2 butterfly, a decimation digital filter, and of an arithmetic unit for digital beam forming. The 8×8-bit RSFQ multiplier uses a two- level parallel carry- save reduction tree that significantly reduces the multiplier latency. The 80-GHz carry-save reduction is implemented with asynchronous data-driven wave pipelined [4:2] compressors built with toggle flip-flop cells.
In this article, 8-bit bit-slice butterfly processing units (BPUs) are proposed for 64-point rapid single-flux-quantum (RSFQ) fast Fourier transform processors. The BPUs are based on radix-2, mixed-radix, and split-radix algorithms, respectively. Unlike the previously developed bit-serial RSFQ BPUs, the proposed bit-slice BPUs continuously process 64-point data divided into eight slices of eight points each in order to reduce the hardware cost. The BPUs use synchronous concurrent-flow clocking and they can be extended to any n2-point processing.
We have designed and RSFQ multiplier-accumulator, the central component of our decimation digital filter. The circuit consists of 38 synchronous RSFQ cells of six types arranged into a rectangular systolic array fed by one parallel input and one serial input. Timing is based on counter-flow clock distribution scheme with simulated maximum clock frequency of 11 GHz. The circuit, fabricated at Hypres, Inc., contains 1100 Josephson junctions, has power consumption less than 0.2 mW, and area less than 2.5 mm/sup 2/. The multiplier-accumulator has been tested at low frequency demonstrating full functionality and stable operation over a 24 hour testing period. This four-bit multiplier accumulator is one of the largest reported RSFQ circuits verified experimentally to date.
We have designed a Rapid Single-Flux-Quantum (RSFQ) bit-serial real-time pipeline multiplier for digital signal processing (DSP) applications. A single-bit module of this multiplier consists of 96 Josephson junctions and uses a B-flip-flop-based carry-save adder (CSA). For HYPRES' standard 1-kA/cm/sup 2/ Nb process with 3.5 /spl mu/m-diameter Josephson junctions the module occupies all area of 350/spl times/600 /spl mu/m/sup 2/. Simulations show that the circuit should dissipate 28 /spl mu/W of power at 2.6 mV dc supply voltage and operate at frequencies of up to 25 GHz. We have successfully tested all cells of the module and verified correct operation of a simplified version of the module at low frequencies. According to numerical simulations, the speed of the multiplier is limited by the CSA. In order to overcome this bottleneck we have developed a concept of a fast carry-save pipeline adder based on XOR gates which uses an RSFQ-specific algorithm for carry bit calculation.>
We report the preliminary designs and the experimental results of high-speed digital processing elements based on phase-mode logic circuits. The core cell of these elements is a bit-serial adder cell consisting of the ICF gate which is the basic gate of phase-mode logic. Our main target is the application of the logic circuits to Digital Signal Processing. The basic arithmetic operations of DSP are a multiplication and an addition. Basic concept of the phase-mode pipelined parallel multiplier has been proposed previously. We design a 2 /spl times/ 2 AND array block and a 2-bit ripple-carry adder for the primitive parallel pipelined multiplier and also a 2-bit subtractor with a pipelined structure. These processing elements have been fabricated using NEC standard 2.5 kA/cm/sup 2/ Nb/AlOx/Nb process. The low-speed test results of these elements show correct operations. Numerical simulations show that a carry save adder (a 2-bit ripple carry adder) can operate over 10 GHz. We also discuss the prospects of large-scale SFQ DSP based on Nb junction technology.