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IEICE Technical Report; IEICE Tech. Rep.

Study on Passive Transmission Lines Used in Low-Voltage-Biased RSFQ Circuit

Takumi Takinami, Masato Ito, Kitayama Atsushi, Masamitsu Tanaka, Akira Fujimaki

Published Jul 12, 2012• 0 citations
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Related papers

低電圧駆動SFQ回路におけるPTL配線技術の検討

Takumi Takinami, MASATO ITO, Atsushi KITAYAMA +6 more

We have studied on Passive Transmission Line technique used in rapid-single-flux-quantum(RSFQ) circuits biased by low voltages. The power consumption of RSFQ circuits is able to reduce by lowing bias voltages. Even in the RSFQ, the PTLs are essential for obtaining high-speed, further low energy consumption. We designed the PTL on the high-speed test and measured the width of bias current margin and maximum operating frequency. As a result, the circuits output the timing error. We speculate the reason of this error. One bias current flowed in other bias line in low voltage area. So, we analyze it used by simulation.

•Jul 1, 2012•0 citations

△Evaluation of Interference in Low-Voltage RSFQ Circuits

Takumi Takinami

The Japan Society of Applied Physics•Feb 13, 2013•0 citations

Characteristics of driver and receiver circuits with a passive transmission line in RSFQ circuits

Hideo Suzuki, Shuichi Nagasawa, Kazunori Miyahara +1 more

We report simulated results of-rapid single flux quantum (SFQ) circuits having driver, receiver, and passive transmission lines for propagating SFQ pulses to investigate the design criteria. We have studied the equivalent input/output resistance of the driver/receiver in various bias conditions and found that the resistance is almost proportional to the bias current of the driver/receiver. Furthermore, we have proposed inserting a series resistor at the end of the superconducting passive transmission line (PTL) for avoiding undesirable flux trapping in the loop and for isolation in regard to the DC current. We also found that the reduction of the bias margin due to the resistance is rather small when the resistance is much smaller than the impedance of the PTL. An operating margin of more than 30% was obtained in the driver/receiver circuits including the PTL and the series resistor.

IEEE Transactions on Applied Superconductivity•Jan 1, 2000•30 citations

Passive Transmission Lines at Ultimate Clock Frequencies of SFQ Circuits

Sasan Razmkhah, Pascal Febvre

•Sep 1, 2019•0 citations

Interconnect Routing for Large-Scale RSFQ Circuits

Tahereh Jabbari, Gleb Krylov, Stephen R. Whiteley +3 more

The increasing complexity of modern rapid single flux quantum (RSFQ) circuits has made on-chip signal routing, an issue of growing importance. In this paper, several methods for routing large-scale RSFQ circuits are described, and a process is presented for determining when to use passive microstrip transmission lines (PTL) and active Josephson transmission lines (JTL). The effect of the size of the JTL inductor and Josephson junctions on the length of a JTL chain for a target delay is also discussed. The dependence of the JTL inductance on the physical layout is evaluated, and the effects of the primary PTL parameters on delay are characterized. A novel PTL driver and receiver configuration is also proposed. Tradeoffs among the number of JJs, inductance, and length of a PTL stripline in the receiver and driver circuits are reported. The energy dissipation is evaluated for two different interconnects. A tradeoff between the proposed PTL circuits and an optimized JTL in terms of energy dissipation and delay is discussed. Guidelines for choosing the optimal element values are determined, and a simulated bias margin of ±29% for the bias current of the proposed receiver operating at 20 GHz in a 10 kA/cm2technology for a 1-mm transmission line is achieved. Summarizing, guidelines and design tradeoffs appropriate for automated layout and synthesis are provided for driving long interconnect in SFQ VLSI circuits.

IEEE Transactions on Applied Superconductivity•Mar 4, 2019•86 citations

Evaluation of Low-Voltage RSFQ Circuits Using Unshunted Junctions

Masamitsu Tanaka

The Japan Society of Applied Physics•Feb 13, 2013•0 citations
We have studied on Passive Transmission Line technique used in rapid-single-flux-quantum(RSFQ) circuits biased by low voltages. The power consumption of RSFQ circuits is able to reduce by lowing bias voltages. Even in the RSFQ, the PTLs are essential for obtaining high-speed, further low energy consumption. We designed the PTL on the high-speed test and measured the width of bias current margin and maximum operating frequency. As a result, the circuits output the timing error. We speculate the reason of this error. One bias current flowed in other bias line in low voltage area. So, we analyze it used by simulation.
We report simulated results of-rapid single flux quantum (SFQ) circuits having driver, receiver, and passive transmission lines for propagating SFQ pulses to investigate the design criteria. We have studied the equivalent input/output resistance of the driver/receiver in various bias conditions and found that the resistance is almost proportional to the bias current of the driver/receiver. Furthermore, we have proposed inserting a series resistor at the end of the superconducting passive transmission line (PTL) for avoiding undesirable flux trapping in the loop and for isolation in regard to the DC current. We also found that the reduction of the bias margin due to the resistance is rather small when the resistance is much smaller than the impedance of the PTL. An operating margin of more than 30% was obtained in the driver/receiver circuits including the PTL and the series resistor.
The increasing complexity of modern rapid single flux quantum (RSFQ) circuits has made on-chip signal routing, an issue of growing importance. In this paper, several methods for routing large-scale RSFQ circuits are described, and a process is presented for determining when to use passive microstrip transmission lines (PTL) and active Josephson transmission lines (JTL). The effect of the size of the JTL inductor and Josephson junctions on the length of a JTL chain for a target delay is also discussed. The dependence of the JTL inductance on the physical layout is evaluated, and the effects of the primary PTL parameters on delay are characterized. A novel PTL driver and receiver configuration is also proposed. Tradeoffs among the number of JJs, inductance, and length of a PTL stripline in the receiver and driver circuits are reported. The energy dissipation is evaluated for two different interconnects. A tradeoff between the proposed PTL circuits and an optimized JTL in terms of energy dissipation and delay is discussed. Guidelines for choosing the optimal element values are determined, and a simulated bias margin of ±29% for the bias current of the proposed receiver operating at 20 GHz in a 10 kA/cm2technology for a 1-mm transmission line is achieved. Summarizing, guidelines and design tradeoffs appropriate for automated layout and synthesis are provided for driving long interconnect in SFQ VLSI circuits.