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低電圧駆動SFQ回路におけるPTL配線技術の検討

Takumi Takinami, MASATO ITO, Atsushi KITAYAMA, Masamitsu Tanaka, Akira Fujimaki, Masato ITO, 敦史 北山, Masamitsu Tanaka, 藤巻朗

Published Jul 1, 2012• 0 citations
OpenAlex

Abstract

We have studied on Passive Transmission Line technique used in rapid-single-flux-quantum(RSFQ) circuits biased by low voltages. The power consumption of RSFQ circuits is able to reduce by lowing bias voltages. Even in the RSFQ, the PTLs are essential for obtaining high-speed, further low energy consumption. We designed the PTL on the high-speed test and measured the width of bias current margin and maximum operating frequency. As a result, the circuits output the timing error. We speculate the reason of this error. One bias current flowed in other bias line in low voltage area. So, we analyze it used by simulation.

Related papers

Characteristics of driver and receiver circuits with a passive transmission line in RSFQ circuits

Hideo Suzuki, Shuichi Nagasawa, Kazunori Miyahara +1 more

We report simulated results of-rapid single flux quantum (SFQ) circuits having driver, receiver, and passive transmission lines for propagating SFQ pulses to investigate the design criteria. We have studied the equivalent input/output resistance of the driver/receiver in various bias conditions and found that the resistance is almost proportional to the bias current of the driver/receiver. Furthermore, we have proposed inserting a series resistor at the end of the superconducting passive transmission line (PTL) for avoiding undesirable flux trapping in the loop and for isolation in regard to the DC current. We also found that the reduction of the bias margin due to the resistance is rather small when the resistance is much smaller than the impedance of the PTL. An operating margin of more than 30% was obtained in the driver/receiver circuits including the PTL and the series resistor.

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消費電力数nWの単一磁束量子回路の動作実証

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We have demonstrated rapid-single-flux-quantum (RSFQ) circuits with reduced power consumptions by lowering bias voltages and critical currents. The power consumption including a power consumption of a bias resistor is measured to be around 1 nW/JJ in 8-bit shift registers, while the operating frequency ranges from 7.5 GHz to 20 GHz. we lower bias voltages applied to RSFQ circuits. The values of bias resistances are proportional to bias voltages. At lowered bias voltages, the power consumption of the bias resistor is reduced. When a voltage begins to be generated at a Josephson junction, the net current provided to the junction and to the shunt resistor is decreased. As a result, the magnitude of the voltage is suppressed, and the power consumption of the shunt resistor is reduced. The power energy-delay product is about 70 times smaller and the the energy-delay product is more than 13 times smaller than that of the conventional RSFQ circuits. Low poewer SFQ circuits are superior in terms of energy-delay product to semiconductor circuits though the power consumption of SFQ cicuits contains the refrigerating machine.

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Repeater Insertion in SFQ Interconnect

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Along with the improvement of integration and the requirement of high-speed operation, the passive transmission line (PTL) plays a significant role in superconducting integrated circuits due to its intrinsic advantage of extremely low propagation delay and low signal loss in long-distance transmission. Good impedance matching is critical to reduce the signal reflection in the transmission line and maximize the power transferred. Based on the PTL wiring layer selection under SIMIT-Nb03 process, we studied the equivalent input/output impedance for Josephson junction (JJ) at the IO port and explored a method of impedance matching in rapid-single-flux-quantum circuits by adjusting the Stewart McCumber parameter${\beta }_{\bm{C}}$of the JJ in the design of the PTL's driver and receiver. Furthermore, the accompanying influence from JJ's modified${\beta }_{\bm{C}}$on the performance of the driver and receiver is evaluated to maximize the profit of the functional circuits. The common-used serial resistor is removed to obtain a balanced bias margin for the PTL circuits. The proposed PTL has been designed and tested based on SIMIT-Nb03 fabrication process. In total,$ \pm $30% bias margin for the PTL is achieved at low frequency and high frequency (40 GHz) contrast tests, including operation speed and transmission length as test vector. Additionally, a frequency sweep for 1 mm PTL is performed by the designed ring oscillator on the chip. The maximum working frequency is up to 129 GHz, with a margin duration of 8%.

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Ashish Shukla, Benjamin Chonigman, Anubhav Sahu +3 more

As the complexity of superconductor circuits grows, we envision a dense network of passive transmission lines (PTLs) being used to interconnect cells in rapid-single-flux-quantum (RSFQ) circuits. In our library approach, each cell has dedicated tracks as place holders for routing PTLs. Higher impedance PTLs are desirable due to their narrower width. However, at higher impedance, the margins for the PTL receiver degrade rapidly. We have designed, fabricated, tested, and simulated passive transmission lines (PTLs) for high-speed interconnects in the MIT-LL SFQ5ee 10 kA/cm2process. For the symmetric dual ground planes case, PTLs are in the M1 layer with M0 and M2 ground planes, or in the M3 layer with M2 and M4 ground planes. For the asymmetrical dual ground planes case, PTLs are in M2 or M3 layers with M1 and M4 ground planes. We report ±30% margins for these PTLs. We investigate the receiver margins for these PTLs and report impact of margins as a function of corners, interlayer transitions, variants of drivers, and receivers. We demonstrate 100 GHz PTL operation in ring oscillator measurements. We have also adopted multi-layer multi-conductor transmission line models for PTL simulation. We observe good model-to-hardware correlation for low- and high-frequency operation.

IEEE Transactions on Applied Superconductivity•Mar 8, 2019•30 citations
We have studied on Passive Transmission Line technique used in rapid-single-flux-quantum(RSFQ) circuits biased by low voltages. The power consumption of RSFQ circuits is able to reduce by lowing bias voltages. Even in the RSFQ, the PTLs are essential for obtaining high-speed, further low energy consumption. We designed the PTL on the high-speed test and measured the width of bias current margin and maximum operating frequency. As a result, the circuits output the timing error. We speculate the reason of this error. One bias current flowed in other bias line in low voltage area. So, we analyze it used by simulation.
We report simulated results of-rapid single flux quantum (SFQ) circuits having driver, receiver, and passive transmission lines for propagating SFQ pulses to investigate the design criteria. We have studied the equivalent input/output resistance of the driver/receiver in various bias conditions and found that the resistance is almost proportional to the bias current of the driver/receiver. Furthermore, we have proposed inserting a series resistor at the end of the superconducting passive transmission line (PTL) for avoiding undesirable flux trapping in the loop and for isolation in regard to the DC current. We also found that the reduction of the bias margin due to the resistance is rather small when the resistance is much smaller than the impedance of the PTL. An operating margin of more than 30% was obtained in the driver/receiver circuits including the PTL and the series resistor.
We have demonstrated rapid-single-flux-quantum (RSFQ) circuits with reduced power consumptions by lowering bias voltages and critical currents. The power consumption including a power consumption of a bias resistor is measured to be around 1 nW/JJ in 8-bit shift registers, while the operating frequency ranges from 7.5 GHz to 20 GHz. we lower bias voltages applied to RSFQ circuits. The values of bias resistances are proportional to bias voltages. At lowered bias voltages, the power consumption of the bias resistor is reduced. When a voltage begins to be generated at a Josephson junction, the net current provided to the junction and to the shunt resistor is decreased. As a result, the magnitude of the voltage is suppressed, and the power consumption of the shunt resistor is reduced. The power energy-delay product is about 70 times smaller and the the energy-delay product is more than 13 times smaller than that of the conventional RSFQ circuits. Low poewer SFQ circuits are superior in terms of energy-delay product to semiconductor circuits though the power consumption of SFQ cicuits contains the refrigerating machine.
Superconductive passive transmission lines (PTL) are widely used for signal routing in large-scale rapid single flux quantum (RSFQ) circuits. Due to the imperfect matching of the transmission lines between the driver and receiver, single flux quantum (SFQ) pulses are partially reflected. The round trip propagation time of these reflections can coincide with the following SFQ pulse, resulting in a decrease in bias margins or incorrect circuit behavior. This resonant effect depends upon the length of the PTL and the clock frequency of the signal. A methodology to reduce and manage this effect is the focus of this article. A closed-form expression describing the dependence of the resonance frequency on the length of the PTL is presented. This expression describes a set of forbidden lengths for PTL interconnect segments in RSFQ circuits. The proposed methodology and algorithm insert active PTL-based repeaters into long superconductive interconnect while ensuring the length of the line segment is outside the forbidden region and increasing bias margins.
Along with the improvement of integration and the requirement of high-speed operation, the passive transmission line (PTL) plays a significant role in superconducting integrated circuits due to its intrinsic advantage of extremely low propagation delay and low signal loss in long-distance transmission. Good impedance matching is critical to reduce the signal reflection in the transmission line and maximize the power transferred. Based on the PTL wiring layer selection under SIMIT-Nb03 process, we studied the equivalent input/output impedance for Josephson junction (JJ) at the IO port and explored a method of impedance matching in rapid-single-flux-quantum circuits by adjusting the Stewart McCumber parameterβC{\beta }_{\bm{C}}βC​of the JJ in the design of the PTL's driver and receiver. Furthermore, the accompanying influence from JJ's modifiedβC{\beta }_{\bm{C}}βC​on the performance of the driver and receiver is evaluated to maximize the profit of the functional circuits. The common-used serial resistor is removed to obtain a balanced bias margin for the PTL circuits. The proposed PTL has been designed and tested based on SIMIT-Nb03 fabrication process. In total,$ \pm $30% bias margin for the PTL is achieved at low frequency and high frequency (40 GHz) contrast tests, including operation speed and transmission length as test vector. Additionally, a frequency sweep for 1 mm PTL is performed by the designed ring oscillator on the chip. The maximum working frequency is up to 129 GHz, with a margin duration of 8%.
We propose an inductance-load-biasing method in order to reduce power consumption of rapid single flux quantum (SFQ) logic circuits. The main idea arises from the fact that a current source can be made of a large inductor accompanied by a large flux. In our proposal, the current source is composed of a large inductor L b , a small resistor R b and a small voltage source V b . Computer simulations of inductance-load-biased Josephson transmission lines (JTLs) show that an SFQ pulse propagates correctly when L b is large enough even if R b is very small. In order to implement the inductance-load-biased JTL, we have made two different layouts: one uses a large bias inductance L b of a typical stripline structure on a ground plane which occupies a rather large area; the other uses L b in the shape of a coplanar stripline, which costs a smaller area.
As the complexity of superconductor circuits grows, we envision a dense network of passive transmission lines (PTLs) being used to interconnect cells in rapid-single-flux-quantum (RSFQ) circuits. In our library approach, each cell has dedicated tracks as place holders for routing PTLs. Higher impedance PTLs are desirable due to their narrower width. However, at higher impedance, the margins for the PTL receiver degrade rapidly. We have designed, fabricated, tested, and simulated passive transmission lines (PTLs) for high-speed interconnects in the MIT-LL SFQ5ee 10 kA/cm2process. For the symmetric dual ground planes case, PTLs are in the M1 layer with M0 and M2 ground planes, or in the M3 layer with M2 and M4 ground planes. For the asymmetrical dual ground planes case, PTLs are in M2 or M3 layers with M1 and M4 ground planes. We report ±30% margins for these PTLs. We investigate the receiver margins for these PTLs and report impact of margins as a function of corners, interlayer transitions, variants of drivers, and receivers. We demonstrate 100 GHz PTL operation in ring oscillator measurements. We have also adopted multi-layer multi-conductor transmission line models for PTL simulation. We observe good model-to-hardware correlation for low- and high-frequency operation.