Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

The Journal of Supercomputing

OpenCL-based design of an FPGA accelerator for quantum annealing simulation

Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masamichi J. Miyama, Masayuki Ohzeki

Published Feb 20, 2019• 21 citations
Publisher
DOI
10.1007/s11227-019-02778-w

Related papers

FPGA-Based Accelerator Architectures for Large-Scale Quantum Annealing with Fully-Connected Ising Models

Chia Yin Liu

•Mar 30, 2022•0 citations

Design space exploration for an FPGA-based quantum annealing simulator with interaction-coefficient-generators

Chia-Yin Liu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama

The Journal of Supercomputing•May 18, 2021•20 citations

Design of a parallel hardware architecture for Quantum Annealing Algorithm acceleration

Evelina Forno

•Jul 26, 2018•0 citations

Quantum Gate Simulation and Acceleration on FPGA

Nagendra Singh, Abhishek Tiwari, K. Bhagirath +1 more

Lecture notes in electrical engineering•Jan 1, 2026•0 citations

Scalable Quantum Circuit Simulation via Circuit Cutting and FPGA Acceleration

Xiaokun Yang, Xinpeng Li, Jeremy W. Turner +5 more

ACM International Symposium on High-Performance Parallel and Distributed Computing (HPDC)•Jul 11, 2026•0 citations

Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL

Hasitha Muthumala Waidyasooriya, Yusuke Araki, Masanori Hariyama

Quantum annealing (QA) is used to find the global optimum for combinatorial optimization problems. QA can be simulated on a computer using quantum Monte Carlo (QMC) simulation while spending a huge processing time. We propose a custom architecture to accelerate simulated QA. The proposed architecture is implemented using “open computing language (OpenCL)” on an Intel Aria10 FPGA. It is possible to design the most appropriate architecture for different optimization problems by changing the design parameters of the OpenCL code. We achieved over 1.94 times speed-up compared to CPU-based implementation.

International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)•Nov 1, 2018•9 citations
Quantum annealing (QA) is used to find the global optimum for combinatorial optimization problems. QA can be simulated on a computer using quantum Monte Carlo (QMC) simulation while spending a huge processing time. We propose a custom architecture to accelerate simulated QA. The proposed architecture is implemented using “open computing language (OpenCL)” on an Intel Aria10 FPGA. It is possible to design the most appropriate architecture for different optimization problems by changing the design parameters of the OpenCL code. We achieved over 1.94 times speed-up compared to CPU-based implementation.