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ACM International Symposium on High-Performance Parallel and Distributed Computing (HPDC)

Scalable Quantum Circuit Simulation via Circuit Cutting and FPGA Acceleration

Xiaokun Yang, Xinpeng Li, Jeremy W. Turner, Cameron D. DiSomma, Yunhe Feng, Xuechen Zhang, Vipin Chaudhary, Shuai Xu

Published Jul 11, 2026• 0 citations
Publisher
DOI
10.1145/3806645.3816155

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This paper presents a parameterized hardware generator for quantum gate emulation, designed to accelerate quantum circuit simulation through specialized hardware architectures. The generator is implemented in the Chisel hardware construction language, enabling automatic production of synthesizable SystemVerilog code from user-defined design parameters such as floating-point precisions, pipeline depth, and the number of qubits. Functional validation shows the accuracy of the generated designs, while field-programmable gate array (FPGA)-based prototyping demonstrates efficient performance for the emulation of 1 to 4-qubit quantum gates. The results highlight the potential of hardware generation frameworks to provide scalable and flexible acceleration for future quantum circuit research.
This study presents Q2SV, an FPGA‐based quantum state vector simulator implemented using high‐level synthesis (HLS), capable of simulating quantum circuits with up to 29 qubits. Using FPGA parallelism, efficient memory allocation, and hardware‐optimized execution pipelines, Q2SV achieves scalable quantum simulation without requiring iterative resynthesis. The system’s workflow processes OpenQASM circuits by providing a flexible and general‐purpose quantum state vector simulation approach. Experimental evaluations demonstrate significant reductions in execution time and storage requirements, positioning FPGAs as a possible alternative to GPUs and CPUs for large‐scale quantum circuit emulation. While not yet matching the raw computational power of high‐end CPUs and GPUs in all cases, this work establishes a foundational framework for future optimizations in hardware‐accelerated quantum simulation. This work provides an adaptable HLS‐based code that serves as a template that paves the way for enhanced memory management, parallel processing, and architecture‐specific optimizations, enabling more efficient FPGA‐based quantum simulations in the future.