A quantum computing simulation provides the opportunity to explore the behaviors of quantum circuits, study the properties of quantum gates, and develop quantum computing algorithms. Simulating quantum circuits requires geometric time and space complexities, impacting the size of the quantum circuit that can be simulated as well as the respective time required to simulate a particular circuit. Applying the parallelism inherent in the simulation and crafting custom architectures, larger quantum circuits can be simulated. A scalable accelerator architecture is proposed to provide a high performance, highly parallel, accelerator. Among the challenges of creating a scalable architecture is managing parallelism, efficiently routing quantum state components for gate evaluation, and measurement. An example is demonstrated on an Intel Agilex field programmable gate array (FPGA).A quantum computing simulation provides the opportunity to explore the behaviors of quantum circuits, study the properties of quantum gates, and develop quantum computing algorithms. Simulating quantum circuits requires geometric time and space complexities, impacting the size of the quantum circuit that can be simulated as well as the respective time required to simulate a particular circuit. Applying the parallelism inherent in the simulation and crafting custom architectures, larger quantum circuits can be simulated. A scalable accelerator architecture is proposed to provide a high performance, highly parallel, accelerator. Among the challenges of creating a scalable architecture is managing parallelism, efficiently routing quantum state components for gate evaluation, and measurement. An example is demonstrated on an Intel Agilex field programmable gate array (FPGA).

arXiv:2407.06415Jul 8, 20240 citations

Tensor Networks for Simulating Quantum Circuits on FPGAs

Maksim Levental

Most research in quantum computing today is performed against simulations of quantum computers rather than true quantum computers. Simulating a quantum computer entails implementing all of the unitary operators corresponding to the quantum gates as tensors. For high numbers of qubits, performing tensor multiplications for these simulations becomes quite expensive, since $N$ -qubit gates correspond to $2^{N}$ -dimensional tensors. One way to accelerate such a simulation is to use field programmable gate array (FPGA) hardware to efficiently compute the matrix multiplications. Though FPGAs can efficiently perform tensor multiplications, they are memory bound, having relatively small block random access memory. One way to potentially reduce the memory footprint of a quantum computing system is to represent it as a tensor network; tensor networks are a formalism for representing compositions of tensors wherein economical tensor contractions are readily identified. Thus we explore tensor networks as a means to reducing the memory footprint of quantum computing systems and broadly accelerating simulations of such systems.Most research in quantum computing today is performed against simulations of quantum computers rather than true quantum computers. Simulating a quantum computer entails implementing all of the unitary operators corresponding to the quantum gates as tensors. For high numbers of qubits, performing tensor multiplications for these simulations becomes quite expensive, since $N$-qubit gates correspond to $2^{N}$-dimensional tensors. One way to accelerate such a simulation is to use field programmable gate array (FPGA) hardware to efficiently compute the matrix multiplications. Though FPGAs can efficiently perform tensor multiplications, they are memory bound, having relatively small block random access memory. One way to potentially reduce the memory footprint of a quantum computing system is to represent it as a tensor network; tensor networks are a formalism for representing compositions of tensors wherein economical tensor contractions are readily identified. Thus we explore tensor networks as a means to reducing the memory footprint of quantum computing systems and broadly accelerating simulations of such systems.

arXiv:2108.06831Aug 15, 20216 citations

Hardware Generation for Quantum Gate Emulation and Acceleration

Jeremy W. Turner, Cameron D. DiSomma, X. David Zhang +2 more

This paper presents a parameterized hardware generator for quantum gate emulation, designed to accelerate quantum circuit simulation through specialized hardware architectures. The generator is implemented in the Chisel hardware construction language, enabling automatic production of synthesizable SystemVerilog code from user-defined design parameters such as floating-point precisions, pipeline depth, and the number of qubits. Functional validation shows the accuracy of the generated designs, while field-programmable gate array (FPGA)-based prototyping demonstrates efficient performance for the emulation of 1 to 4-qubit quantum gates. The results highlight the potential of hardware generation frameworks to provide scalable and flexible acceleration for future quantum circuit research.This paper presents a parameterized hardware generator for quantum gate emulation, designed to accelerate quantum circuit simulation through specialized hardware architectures. The generator is implemented in the Chisel hardware construction language, enabling automatic production of synthesizable SystemVerilog code from user-defined design parameters such as floating-point precisions, pipeline depth, and the number of qubits. Functional validation shows the accuracy of the generated designs, while field-programmable gate array (FPGA)-based prototyping demonstrates efficient performance for the emulation of 1 to 4-qubit quantum gates. The results highlight the potential of hardware generation frameworks to provide scalable and flexible acceleration for future quantum circuit research.

IEEE ... International Conference on Data Mining workshopsNov 12, 20250 citations

Acceleration of Quantum Algorithm with Multi-qubit Gates

Juha J. Vartiainen, Mikio Nakahara, A. O. Niskanen +1 more

Jan 1, 20030 citations

N

-qubit gates correspond to

2^{N}

-dimensional tensors. One way to accelerate such a simulation is to use field programmable gate array (FPGA) hardware to efficiently compute the matrix multiplications. Though FPGAs can efficiently perform tensor multiplications, they are memory bound, having relatively small block random access memory. One way to potentially reduce the memory footprint of a quantum computing system is to represent it as a tensor network; tensor networks are a formalism for representing compositions of tensors wherein economical tensor contractions are readily identified. Thus we explore tensor networks as a means to reducing the memory footprint of quantum computing systems and broadly accelerating simulations of such systems.