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Scalable Realization of Surface Code Quantum Memory by Applying Multi-Qubit Parity Detector Gates

Sahar Daraeizadeh, Sarah Mostame, Preethika Kumar Eslami, Marek A. Perkowski, Xiaoyu Song B

Published Nov 22, 2018• 0 citations
OpenAlex

Abstract

We analytically designed the control bias pulses to realize new multi-qubit parity detector gates for 2-Dimensional (2D) array of superconducting flux qubits with non-tunable couplings. We designed two 5-qubit gates such that the middle qubit is the target qubit and all four coupled neighbors are the control qubits. These new gates detect the parity between two vertically/horizontally coupled neighbor qubits while cancelling out the coupling effect of horizontally/vertically coupled neighbor qubits. For a 3 by 3 array of 9 qubits with non-tunable couplings, we simulated the effect of our new 5-qubit horizontal and vertical parity detector gates. We achieved the intrinsic fidelity of 99.9% for horizontal and vertical parity detector gates. In this paper we realize Surface Code memories based on the multi-qubit parity detector gates for nearest neighbor superconducting flux qubits with and without tunable couplings. However, our scheme is applicable to other superconducting qubits as well. In our proposed memory realization, error correction cycles can be performed in parallel on several logical qubits or even on the entire 2D array of qubits, this makes it a desirable candidate for large scale and longtime quantum computation. In addition to extensive reduction of the number of control parameters in our method, the error correction cycle time is reduced and does not grow by increasing the number of qubits in the logical qubit layout. Another advantage of this approach is that there will not be any dephasing from idle qubits since all the qubits are used in the error correction cycles.

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We analytically designed the control bias pulses to realize new multi-qubit parity detector gates for 2-Dimensional (2D) array of superconducting flux qubits with non-tunable couplings. We designed two 5-qubit gates such that the middle qubit is the target qubit and all four coupled neighbors are the control qubits. These new gates detect the parity between two vertically/horizontally coupled neighbor qubits while cancelling out the coupling effect of horizontally/vertically coupled neighbor qubits. For a 3 by 3 array of 9 qubits with non-tunable couplings, we simulated the effect of our new 5-qubit horizontal and vertical parity detector gates. We achieved the intrinsic fidelity of 99.9% for horizontal and vertical parity detector gates. In this paper we realize Surface Code memories based on the multi-qubit parity detector gates for nearest neighbor superconducting flux qubits with and without tunable couplings. However, our scheme is applicable to other superconducting qubits as well. In our proposed memory realization, error correction cycles can be performed in parallel on several logical qubits or even on the entire 2D array of qubits, this makes it a desirable candidate for large scale and longtime quantum computation. In addition to extensive reduction of the number of control parameters in our method, the error correction cycle time is reduced and does not grow by increasing the number of qubits in the logical qubit layout. Another advantage of this approach is that there will not be any dephasing from idle qubits since all the qubits are used in the error correction cycles.
We realize Surface Code quantum memories for nearest-neighbor qubits with always-on Ising interactions. This is done by utilizing multi-qubit gates that mimic the functionality of several gates. The previously proposed Surface Code memories rely on error syndrome detection circuits based on CNOT gates. In a two-dimensional planar architecture, to realize a two-qubit CNOT gate in the presence of couplings to other neighboring qubits, the interaction of the target qubit with its three other neighbors must cancel out. Here we present a new error syndrome detection circuit utilizing multi-qubit parity gates. In addition to speed up in the error correction cycles, in our approach, the depth of the error syndrome detection circuit does not grow by increasing the number of qubits in the logical qubit layout. We analytically design the system parameters to realize new five-qubit gates suitable for error syndrome detection in nearest-neighbor two-dimensional array of qubits. The five-qubit gates are designed such that the middle qubit is the target qubit and all four coupled neighbors are the control qubits. In our scheme, only one control parameter of the target qubits must be adjusted to realize controlled-unitary operations. The gate operations are confirmed with a fidelity of >99.9% in a simulated system consists of nine nearest-neighbor qubits.
Multi-qubit parity measurements are at the core of many quantum error correction schemes. Extracting multi-qubit parity information typically involves using a sequence of multiple two-qubit gates. In this paper, we propose a superconducting circuit device with native support for multi-qubit parity-controlled gates (PCG). These are gates that perform rotations on a parity ancilla based on the multi-qubit parity operator of adjacent qubits, and can be directly used to perform multi-qubit parity measurements. The circuit consists of a set of concatenated Josephson ring modulators and effectively realizes a set of transmon-like qubits with strong longitudinal nearest-neighbor couplings. PCGs are implemented by applying microwave drives to the parity ancilla at specific frequencies. We investigate the scheme's performance with numerical simulation using realistic parameter choices and decoherence rates, and find that the device can perform four-qubit PCGs in 30 ns with process fidelity surpassing 99%. Furthermore, we study the effects of parameter disorder and spurious coupling between next-nearest neighboring qubits. Our results indicate that this approach to realizing PCGs constitute an interesting candidate for near-term quantum error correction experiments.
Quantum error correction will be a necessary component towards realizing scalable quantum computers with physical qubits. Theoretically, it is possible to perform arbitrarily long computations if the error rate is below a threshold value. The two-dimensional surface code permits relatively high fault-tolerant thresholds at the ~1% level, and only requires a latticed network of qubits with nearest-neighbor interactions. Superconducting qubits have continued to steadily improve in coherence, gate, and readout fidelities, to become a leading candidate for implementation into larger quantum networks. Here we describe characterization experiments and calibration of a system of four superconducting qubits arranged in a planar lattice, amenable to the surface code. Insights into the particular qubit design and comparison between simulated parameters and experimentally determined parameters are given. Single- and two-qubit gate tune-up procedures are described and results for simultaneously benchmarking pairs of two-qubit gates are given. All controls are eventually used for an arbitrary error detection protocol described in separate work [Corcoles et al., Nature Communications, 6, 2015].
Abstract One of the biggest obstacles to building a large scale quantum computer is the high qubit cost of protecting quantum information. For two-dimensional architectures, the surface code has long been the leading candidate quantum memory, but can require upwards of a thousand physical qubits per logical qubit to reach algorithmically-relevant logical error rates. In this work, we introduce a hierarchical memory formed from surface codes concatenated into high-density parity check codes. These yoked surface codes are arrayed in a rectangular grid, with parity checks (yokes) measured along each row, and optionally along each column, using lattice surgery. Our construction assumes no additional connectivity beyond a nearest-neighbor square qubit grid operating at a physical error rate of 10 −3 . At algorithmically-relevant logical error rates, yoked surface codes use as few as one-third the number of physical qubits per logical qubit as standard surface codes, enabling moderate-overhead fault-tolerant quantum memories in two dimensions.
We present a scalable scheme for executing the error-correction cycle of a monolithic surface-code fabric composed of fast-flux-tuneable transmon qubits with nearest-neighbor coupling. An eight-qubit unit cell forms the basis for repeating both the quantum hardware and coherent control, enabling spatial multiplexing. This control uses three fixed frequencies for all single-qubit gates and a unique frequency detuning pattern for each qubit in the cell. By pipelining the interaction and readout steps of ancilla-based X- and Z-type stabilizer measurements, we can engineer detuning patterns that avoid all second-order transmon-transmon interactions except those exploited in controlled-phase gates, regardless of fabric size. Our scheme is applicable to defect-based and planar logical qubits, including lattice surgery.
Quantum error correction (QEC) is one of the crucial building blocks for developing quantum computers that have significant potential for reaching a quantum advantage in applications. Prominent candidates for QEC are stabilizer codes for which periodic readout of stabilizer operators is typically implemented via successive two-qubit entangling gates, and is repeated many times during a computation. To improve QEC performance, it is thus beneficial to make the stabilizer readout faster and less prone to fault-tolerance-breaking errors. Here we design a 3-qubit CZZ gate for superconducting transmon qubits that maps the parity of two data qubits onto one measurement qubit in a single step. We find that the gate can be executed in a duration of 35 35\,35ns with a fidelity of F=99.96 %=99.96 \, \%=99.96%. To optimize the gate, we use an error model obtained from the microscopic gate simulation to systematically suppress Pauli errors that are particularly harmful to the QEC protocol. Using this error model, we investigate the implementation of this 3-qubit gate in a surface code syndrome readout schedule. We find that for the rotated surface code, the implementation of CZZ gates increases the error threshold by nearly 50\% to ≈1.2 %\approx 1.2\,\%≈1.2% and decreases the logical error rate, in the experimental relevant regime, by up to one order of magnitude, compared to the standard CZ readout protocol. We also show that for the unrotated surface code, strictly fault-tolerant readout schedules can be found. This opens a new perspective for below-threshold surface-code error correction, where it can be advantageous to use multi-qubit gates instead of two-qubit gates to obtain a better QEC performance.