IEEE International Conference on Communication Technology (ICCT)

An efficient post processing scheme to lower the error floor of LDPC decoders

Wenjie Li, Jun Ting Lin, Zhongfeng Wang

Published Oct 1, 2017• 4 citations

Abstract

Low-Density Parity-Check (LDPC) codes have extensive applications in numerous communication systems. However, iterative LDPC decoders may suffer from error floor. In this paper, a low complexity post processing scheme (PPS) is proposed to significantly improve the error correction performance of a Min-Sum based LDPC decoder in the error floor region. Instead of using trapping set elimination algorithms, the proposed PPS introduces perturbations so that a decoder can escape from undesired local maximums. After decoding failure, for these unreliable code bits, the proposed PPS generates carefully modified soft messages, which are employed in the following decoding iterations. Numerical results demonstrate that the presented PPS significantly lowers the error floor for simulated LDPC codes.

DOI: 10.1109/icct.2017.8359616

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