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International Conference on Communication Systems and Network Technologies

Design and Implementation of Low Bit Error Rate of LDPC Decoder

Ashlesha P. Kshirsagar, Sandeep Kakde, Manish Devendra Chawhan, Yogesh Suryawanshi

Published Apr 1, 2015• 1 citation
Publisher

Abstract

Many classes of high-performance Low-density parity check codes are based on parity check matrices composed of permutation sub matrices. The emulation-simulation framework further allows the algorithm and implementation to be iteratively redefined to improve the error floor performance of message passing decoder. Log-Like hood-Ratio (LLR) based Belief-Propagation (BP) algorithm is presented for Low Density Parity Check codes. Numerically accurate representation of check node update computation used in LLR-BP decoding is described. The implementation of Sum-Product algorithm (SPA) within Low Density Parity Check Code (LDPC) decoder is described in this paper and the correction term is used to improve the decoding performance of min-sum algorithm (MSA). Quantization and log-tanh function approximation in sum-product decoder strongly affect which absorbing set dominates in error floor region. For LDPC decoder, bit error rate (BER) decreases with increase in the signal to noise ratio.

DOI
10.1109/csnt.2015.161

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Many classes of high-performance Low-density parity check codes are based on parity check matrices composed of permutation sub matrices. The emulation-simulation framework further allows the algorithm and implementation to be iteratively redefined to improve the error floor performance of message passing decoder. Log-Like hood-Ratio (LLR) based Belief-Propagation (BP) algorithm is presented for Low Density Parity Check codes. Numerically accurate representation of check node update computation used in LLR-BP decoding is described. The implementation of Sum-Product algorithm (SPA) within Low Density Parity Check Code (LDPC) decoder is described in this paper and the correction term is used to improve the decoding performance of min-sum algorithm (MSA). Quantization and log-tanh function approximation in sum-product decoder strongly affect which absorbing set dominates in error floor region. For LDPC decoder, bit error rate (BER) decreases with increase in the signal to noise ratio.
Low-Density Parity check (LDPC) codes offer high-performance error correction near the Shannon limit which employs large code lengths and some iterations in the decoding process. The conventional decoding algorithm of LDPC is the Log Likelihood Ratio based Belief Propagation (LLR BP) which is also known as the `Sum-Product algorithm' which gives the best decoding performance and requires the most computational complexity and implementations with increased hardware complexity. Another simpler variant of this algorithm is used which is known as `min-sum algorithm' which reduces computational complexity as well as hardware complexity but with reduced accuracy. This paper analyzes the reason min-sum algorithm is more prone to errors when compared to the sum-product algorithm, and puts forward two improved algorithms which improve the performance of the min-sum algorithm with comparable algorithmic complexity.
To improve performance and reduce computation complexity of the low-density parity-check (LDPC) codes, a min-sum based differential decoding algorithm is proposed. The main principle is that the messages passing in the bipartite graph of the codes are the probability differences and the updates of the check nodes adopt min sum algorithm. Simulation results show that the proposed algorithm can achieve about 0.4dB performance gain over the UMP BP-Based decoding algorithm at bit error rate (BER) of under an additive white Gaussian noise (AWGN) channel. And it can obtain good performance very close to that of the BP decoding algorithm with much lower complexity.
Low-density parity-check (LDPC) codes are widely used in communication systems. When user messages are encoded by binary LDPC codes and transmitted with higher-order modulations, bits composing the same modulated symbol are generally correlated. Traditional soft-decision decoding algorithms for binary LDPC codes like sum-product algorithm (SPA) and min-sum algorithm (MSA) update messages only based on log-likelihood ratio (LLR) of bits, and correlations introduced by modulation are not utilized. In this paper, symbol-based SPA and MSA (S-SPA and S-MSA) which incorporate symbol-level information in the decoding procedures are proposed to provide an alternative low-cost way to better utilize available information. By narrowing the search space of symbols based on bit-level information, the complexities of the proposed algorithms are independent of modulation order. S-SPA and S-MSA achieve better error-correction performances than SPA and MSA with little additional complexities and S-MSA is friendly to hardware design of LDPC decoder.
This thesis is focused on the design and implementation of binary low-density parity-check (LDPC) code decoders for high-speed modern communication systems. The basic of LDPC codes and the performance and bottlenecks, in terms of complexity and hardware efficiency, of the main soft-decision and hard-decision decoding algorithms (such as Min-Sum, Optimized 2-bit Min-Sum and Reliability-based iterative Majority-Logic) are analyzed. The complexity and performance of those algorithms are improved to allow efficient hardware architectures.\n\nA new decoding algorithm called One-Minimum Min-Sum is proposed. It reduces considerably the complexity of the check node update equations of the Min-Sum algorithm. The second minimum is estimated from the first minimum value by a means of a linear approximation that allows a dynamic adjustment. The Optimized 2-bit Min-Sum algorithm is modified to initialize it with the complete LLR values and to introduce the extrinsic information in the messages sent from the variable nodes. Its variable node equation is reformulated to reduce its complexity. Both algorithms were tested for the (2048,1723) RS-based LDPC code and (16129,15372) LDPC code using an FPGA-based hardware emulator. They exhibit BER performance very close to Min-Sum algorithm and do not introduce early error-floor. \n\nIn order to show the hardware advantages of the proposed algorithms, hardware decoders were implemented in a 90 nm CMOS process and FPGA devices based on two types of architectures: full-parallel and partial-parallel one with horizontal layered schedule. The results show that the decoders are more area-time efficient than other published decoders and that the low-complexity of the Modified Optimized 2-bit Min-Sum allows the implementation of 10 Gbps decoders in current FPGA devices. \n\nFinally, a new hard-decision decoding algorithm, the Historical-Extrinsic Reliability-Based Iterative Decoder, is presented. This algorithm introduces the new idea of considering hard-decision votes as soft-decision to compute the extrinsic information of previous iterations. It is suitable for high-rate codes and improves the BER performance of the previous RBI-MLGD algorithms, with similar complexity.
An improved decoding algorithm for low-density parity-check (LDPC) codes is presented. By taking advantages of the first-term Taylor’s series multiple expansion to approximate the correction term of the Jacobian logarithm used in LLR-SPA (log-likelihood ratio sum-product algorithm), we propose an algorithm which significantly simplifies the check node update computation of the optimal LLR-SPA. Besides, the parameter δ is introduced to determine suitable expansion points. The simulation result shows that the proposed method with ten expansion points when δ is set to 0.01 has almost identical performance compared with ideal SPA algorithm and outperforms both the min-sum algorithm (MS), the offset min-sum algorithm (OMS) and the normalised min-sum algorithm (NMS). The architecture of proposed method is also presented for implementation, which has reduced computational complexity and is feasible for hardware implementation.
Very high data rates and decoding computational complexity place strict constraints in 5G and 6G communications. In this paper, non-uniform Quantized Decoding algorithm is proposed for Low-density Parity Check codes (LDPC). In the proposed algorithm, the check node updating process is carried out using quantization, which reduces complexity. The Sum Product Algorithm (SPA) is iterative message passing decoding techniques offer the optimal performance for LDPC codes. Implementations use message-passing decoding with more precision, results extremely high complexity. In Iterative, message-passing (MP), trapping sets and absorbing sets causes low error floor. In this article non-uniform quantization proposed to overcome dynamic range of values over uniform quantization. Simulation results provide coding gain increases closer to of 0.5 dB in higher SNR and has good error floor at 10−5.