Error floor is one major reason for limited use of low-density parity-check (LDPC) codes in applications requiring very low bit error rate. In this brief, an efficient erasure searching post-processor (ESPP) is proposed to lower the error floor of LDPC codes. Here, when a decoding failure is detected, the most unreliable symbols in the decoder output vector are erased, then their values are re-calculated by solving a system of linear equations with a sparse coefficient matrix. Compared to the state-of-the-art post processors, the ESPP has much lower computation complexity. Simulation results show that the proposed method significantly improves the decoding performance of LDPC codes in the error-floor region. Additionally, a well-optimized hardware architecture is developed for the proposed post-processor. Algorithmic transformation and architecture optimization are well explored to reduce the hardware complexity and latency. Synthesis results demonstrate the effectiveness of the proposed architecture.
Error floor is one major reason for limited use of low-density parity-check (LDPC) codes in applications requiring very low bit error rate. In this brief, an efficient erasure searching post-processor (ESPP) is proposed to lower the error floor of LDPC codes. Here, when a decoding failure is detected, the most unreliable symbols in the decoder output vector are erased, then their values are re-calculated by solving a system of linear equations with a sparse coefficient matrix. Compared to the state-of-the-art post processors, the ESPP has much lower computation complexity. Simulation results show that the proposed method significantly improves the decoding performance of LDPC codes in the error-floor region. Additionally, a well-optimized hardware architecture is developed for the proposed post-processor. Algorithmic transformation and architecture optimization are well explored to reduce the hardware complexity and latency. Synthesis results demonstrate the effectiveness of the proposed architecture.
Low-Density Parity-Check (LDPC) codes have extensive applications in numerous communication systems. However, iterative LDPC decoders may suffer from error floor. In this paper, a low complexity post processing scheme (PPS) is proposed to significantly improve the error correction performance of a Min-Sum based LDPC decoder in the error floor region. Instead of using trapping set elimination algorithms, the proposed PPS introduces perturbations so that a decoder can escape from undesired local maximums. After decoding failure, for these unreliable code bits, the proposed PPS generates carefully modified soft messages, which are employed in the following decoding iterations. Numerical results demonstrate that the presented PPS significantly lowers the error floor for simulated LDPC codes.
The error floor phenomenon, associated with iterative decoders, is one of the most significant limitations to the applications of low-density parity-check (LDPC) codes. A variety of techniques from code design to decoder implementation have been proposed to address the error floor problem, among which post-processors have shown to be both effective and implementation-friendly. In this paper, we take the inspiration from simulated annealing to generalize the post-processor design using three methods: quenching, extended heating, and focused heating, each of which targets a different error structure. The resulting post-processor is demonstrated to lower the error floors by two orders of magnitude for two structured code examples, a (2209, 1978) array LDPC code and a (1944, 1620) LDPC code used by the IEEE 802.11n standard. The post-processor can be integrated with a belief-propagation decoder with minimal overhead. The post-processor design is equally applicable to other structured LDPC codes.
After the introduction of iterative coding, Low Density Parity Check (LDPC) codes have received a lot of attention due to their remarkable near Shannon-limit performance and practical decoder implementation. However, when employing an LDPC code for various applications, multiple issues do arise at the simulation, algorithm and implementation levels. The first issue is the performance evaluation of the iterative LDPC decoder in the very low Bit Error Rate (BER) regions. So far, no analytical tool has been developed to evaluate the performance of LDPC codes. Unfortunately standard Monte Carlo (MC) simulations cannot be used for performance estimation in these low BER regions due to prohibitive execution times. The second issue is the efficiency of the decoding algorithm. Due to the presence of short cycles in the bipartite graph, sum-product decoding algorithms lead to considerable performance loss for short block-length LDPC codes and produce error floors for longer codes. In addition, the iterative processing and estimation of soft probabilistic values with these algorithms result in very high computational complexity, which in turn impedes the adoption of LDPC codes for power constrained systems. Another prime objective is to design a high throughput decoder architecture which is capable of supporting multiple rates and variable code lengths within minimal area.
This work aims to address and provide solutions to the above problems. As a solution to the performance estimation problem of LDPC codes, a highly efficient and novel fast BER simulation technique is developed. At the algorithm level, a performance improvement and error floor avoidance method is introduced, and a computationally efficient algorithm is developed for the sum-product decoding of LDPC codes. And finally, at the architecture level, a high throughput multi-rate variable code length implementation is presented which, when implemented, efficiently minimizes device resources while alleviating the routing complexity of the decoder.
Low Density Parity Check (LDPC) codes are considered to be one of the best classes of error-correcting codes. This thesis deals with two major issues in LDPC codes: decoder design to enhance error correction performance and efficient decoder implementation. Five techniques have been introduced in this thesis. First, an efficient platform for LDPC code design and performance evaluation is developed. This platform implements parallel simulation algorithms to efficiently evaluate the performance of the proposed algorithms for LDPC decoders and code design. Second, an innovative technique is introduced to improve the performance of LDPC decoding in the error-floor region. Special structures in the code graph, called trapping sets, are considered to be the major source of decoding errors in the error-floor region. The proposed technique is based on eliminating the negative effect of trapping sets during LDPC decoding. As a third contribution, a novel approach to improve the decoder performance and/or throughput is introduced. This approach is based on utilizing LDPC decoder idle times by introducing two queues: one at the decoder input and the other at the decoder output. This architecture enables the decoder to run extra iterations beyond the conventional maximum allowable iterations. The fourth proposed technique reduces the bit error rate of LDPC decoders. This technique is based on tracking the number of failed parity check equations in the intermediate decoding iterations, rather than only relying on the final decoder output (after reaching the maximum number of iterations). The last proposed technique deals with the construction of interconnect efficient fully-parallel LDPC codes with high error correction performance. Fully-parallel implementation is very hard due to the complexity of processing elements interconnections. The proposed technique is based on constructing LDPC codes with less complex interconnections and with low impact on the error correction performance. This goal is achieved by putting a constraint on the maximum connection length between any two processing elements.
Low-density parity-check (LDPC) codes are widely used in a variety of communication systems because of their low complexity iterative decoding and performance approaching Shannon capacity. However, the existence of error floor seriously hinders the application and development of LDPC codes in related fields. In this paper, a deep learning-aided post-processing scheme (DLAPPS) based on Layered Normalized Min-Sum algorithm (LNMSA) is proposed to effectively lower error floor of LDPC codes. LNMSA is used in the first stage, and in the second stage incorrect frames are re-decoded by processing two types of nodes classified by neural networks. Simulation results show that the proposed DLAPPS can significantly improve error correction performance and lower the error floor of LDPC codes while maintaining a relatively low decoding complexity.
Assuming iterative decoding for binary erasure channels (BECs), a novel tree-based technique for upper bounding the bit error rates (BERs) of arbitrary, finite low-density parity-check (LDPC) codes is provided and the resulting bound can be evaluated for all operating erasure probabilities, including both the waterfall and the error floor regions. This upper bound can also be viewed as a narrowing search of stopping sets, which is an approach different from the stopping set enumeration used for lower bounding the error floor. When combined with optimal leaf-finding modules, this upper bound is guaranteed to be tight in terms of the asymptotic order. The Boolean framework proposed herein further admits a composite search for even tighter results. For comparison, a refinement of the algorithm is capable of exhausting all stopping sets of size les 13 for irregular LDPC codes of length n ap 500, which requires (13500) ap 1.67 times 1025trials if a brute force approach is taken. These experiments indicate that this upper bound can be used both as an analytical tool and as a deterministic worst-performance (error floor) guarantee, the latter of which is crucial to optimizing LDPC codes for extremely low BER applications, e.g., optical/satellite communications