One of the most significant barriers for using Low Density Parity Check (LDPC) codes in many wireless communication system and magnetic storage devices is the bit error rate floor phenomena with their complex message passing iterative algorithm. LDPC codes are mostly used in communication system because of its outstanding performance achievement. There are various decoding algorithm for LDPC decoder. In this paper, we presented the mathematical analysis of Minimum Weight Decoding (MWD) algorithm and its error rate performance over Additive White Gaussian Noise (AWGN) channel. A comparison of bit error rate performance over signal to noise ratio (dB) is carried out for different codes such as hamming code, BCH code and LDPC code. This paper shows bit error performance of decoder using minimum weight decoding algorithm. The main significance of this paper is that it shows efficient performance of Minimum Weight Decoding (MWD) algorithm based LDPC Decoder. We presented three classes of codes (1) hamming code, (2) BCH code and (3) LDPC Codes. We demonstrate the effectiveness of LDPC decoder over other two code decoders for the code rate 1/2 and block length (16,8) which is tarnished for its error floors.
One of the most significant barriers for using Low Density Parity Check (LDPC) codes in many wireless communication system and magnetic storage devices is the bit error rate floor phenomena with their complex message passing iterative algorithm. LDPC codes are mostly used in communication system because of its outstanding performance achievement. There are various decoding algorithm for LDPC decoder. In this paper, we presented the mathematical analysis of Minimum Weight Decoding (MWD) algorithm and its error rate performance over Additive White Gaussian Noise (AWGN) channel. A comparison of bit error rate performance over signal to noise ratio (dB) is carried out for different codes such as hamming code, BCH code and LDPC code. This paper shows bit error performance of decoder using minimum weight decoding algorithm. The main significance of this paper is that it shows efficient performance of Minimum Weight Decoding (MWD) algorithm based LDPC Decoder. We presented three classes of codes (1) hamming code, (2) BCH code and (3) LDPC Codes. We demonstrate the effectiveness of LDPC decoder over other two code decoders for the code rate 1/2 and block length (16,8) which is tarnished for its error floors.
Low density parity check codes nowadays use in modern system due to their excellent performance. There are different message passing algorithm for LDPC codes to decode. In this paper, we have mention bit flip algorithm in brief and gave its bit error performance over AWGN channel via simulation result. For this communication, we use BPSK i.e. Binary phase shift keying digital modulation technique. This algorithm is based on binary decision message passing algorithm. This paper shows bit error performance of bit flip algorithm for different block lengths of LDPC code. The significance of showing bit error performance in this paper is that it shows how efficiently this algorithm works. We have also mention why BPSK modulation technique is more efficient than any other modulation technique.
Channel coding technique is a fundamental building block in any modern communication system to realize reliable, fast, and secure data transmission. At the same time, it is a challenging and crucial task, as the data transmission happens in a channel where noise, fading, and other impairments are present. The Low-Density Parity-Check (LDPC) codes give substantial results close to the Shannon limit when the complexity and processing delay time are unlimited. In this paper, the performance of the LDPC decoding with four algorithms was investigated. The investigated four algorithms were Belief Propagation (BP), Layered Belief Propagation (LBP), Normalized min-sum (NMS), and Offset min-sum (OMS). These algorithms were examined for code rates ranging from 1/3 to 9/10 and message block lengths (64, 512, 1024, and 5120) bits. The simulation results revealed the flexibility of these decoders in supporting these code rates and block lengths, which enables their usage in a wide range of applications and scenarios for fifth-generation (5G) wireless communication. In addition, the effect of the maximum number of decoding iterations on the error correction performance was investigated, and a gain of 5.6 dB can be obtained by using 32 decoding iterations at BER=2*10-3 instead of one decoding iteration. The results showed that the decoders performed better for longer message blocks than for short message blocks, and less power was required for transmitting longer messages. Finally, the comparison results of their performance in terms of bit error rate (BER) under the same conditions showed a gain of 0.8 dB using LBP at BER= 10-5 compared with the NMS decoding algorithm.
Error correcting codes are used in virtually all communication systems to ensure reliable transmission of information. In 1948, Shannon established an upper-bound on the maximum rate at which information can be transmitted reliably over a noisy channel. Reliably transmitting information with a rate close to this theoretical limit, known as the channel capacity, has been the goal of channel coding scientists for the last five decades. The rediscovery of low-density parity-check (LDPC) codes in the 1990s added much-renewed excitement in the coding community. LDPC codes are interesting because they can approach channel capacity under sub-optimum decoding algorithms whose complexity is linear in the code length. Unsurprisingly, LDPC codes quickly attained their popularity in practical applications such as magnetic storage, wireless and optical communications. One, if not the most, important and challenging problem in LDPC code research is the study and analysis of the error floor phenomenon. This phenomenon is described as an abrupt degradation in the frame error rate performance of LDPC codes in the high signal-to-noise ratio region. Error floor is harmful because its presence prevents the LDPC decoder from reaching very low probability of decoding failure, an important requirement for many applications. Not long after the rediscovery of LDPC codes, scientists established that error floor is caused by certain harmful structures, most commonly known as trapping sets, in the Tanner representation of a code. Since then, the study of error floor mostly consists of three major problems: 1) estimating error floor; 2) constructing LDPC codes with low error floor and 3) designing decoders that are less susceptible to error floor. Although some parts of this dissertation can be used as important elements in error floor estimation, our main contributions are a novel method for constructing LDPC codes with low error floor and a novel class of low complexity decoding algorithms that can collectively alleviate error floor. These contributions are summarized as follows. A method to construct LDPC codes with low error floors on the binary symmetric channel is presented. Codes are constructed so that their Tanner graphs are free of certain small trapping sets. These trapping sets are selected from the Trapping Set Ontology for the Gallager A/B decoder. They are selected based on their relative harmfulness for a given decoding algorithm. We evaluate the relative harmfulness of different trapping sets for the sum-product algorithm by using the topological relations among them and by analyzing the decoding failures on one trapping set in the presence or absence of other trapping sets. We apply this method to construct structured LDPC codes. To facilitate the discussion, we give a new description of structured LDPC codes whose parity-check matrices are arrays of permutation matrices. This description uses Latin squares to define a set of permutation matrices that have disjoint support and to derive a simple necessary and sufficient condition for the Tanner graph of a code to be free of four-cycles. A new class of bit flipping algorithms for LDPC codes over the binary symmetric channel is proposed. Compared to the regular (parallel or serial) bit flipping algorithms, the proposed algorithms employ one additional bit at a variable node to represent its "strength." The introduction of this additional bit allows an increase in the guaranteed error correction capability. An additional bit is also employed at a check node to capture information which is beneficial to decoding. A framework for failure analysis and selection of two-bit bit flipping algorithms is provided. The main component of this framework is the (re)definition of trapping sets, which are the most "compact" Tanner graphs that cause decoding failures of an algorithm. A recursive procedure to enumerate trapping sets is described. This procedure is the basis for selecting a collection of algorithms that work well together. It is demonstrated that decoders which employ a properly selected group of the proposed algorithms operating in parallel can offer high speed and low error floor decoding.
Low-Density Parity-Check (LDPC) codes are error correcting codes with good performance in communications systems. LDPC codes, however, have heavy computational complexity. In this paper, we find out how many iterations are required for sufficient performance of LDPC codes. The Additive White Gaussian Noise (AWGN) channel model and a log-domain Sum-Product (SP) algorithm are used. Experiments measure Bit Error Rate (BER) at each iteration in given SNRs. The result of performance evaluation, the best performance is showed when the number of iteration is 25 at 5 ㏈.
Many classes of high-performance Low-density parity check codes are based on parity check matrices composed of permutation sub matrices. The emulation-simulation framework further allows the algorithm and implementation to be iteratively redefined to improve the error floor performance of message passing decoder. Log-Like hood-Ratio (LLR) based Belief-Propagation (BP) algorithm is presented for Low Density Parity Check codes. Numerically accurate representation of check node update computation used in LLR-BP decoding is described. The implementation of Sum-Product algorithm (SPA) within Low Density Parity Check Code (LDPC) decoder is described in this paper and the correction term is used to improve the decoding performance of min-sum algorithm (MSA). Quantization and log-tanh function approximation in sum-product decoder strongly affect which absorbing set dominates in error floor region. For LDPC decoder, bit error rate (BER) decreases with increase in the signal to noise ratio.
After the introduction of iterative coding, Low Density Parity Check (LDPC) codes have received a lot of attention due to their remarkable near Shannon-limit performance and practical decoder implementation. However, when employing an LDPC code for various applications, multiple issues do arise at the simulation, algorithm and implementation levels. The first issue is the performance evaluation of the iterative LDPC decoder in the very low Bit Error Rate (BER) regions. So far, no analytical tool has been developed to evaluate the performance of LDPC codes. Unfortunately standard Monte Carlo (MC) simulations cannot be used for performance estimation in these low BER regions due to prohibitive execution times. The second issue is the efficiency of the decoding algorithm. Due to the presence of short cycles in the bipartite graph, sum-product decoding algorithms lead to considerable performance loss for short block-length LDPC codes and produce error floors for longer codes. In addition, the iterative processing and estimation of soft probabilistic values with these algorithms result in very high computational complexity, which in turn impedes the adoption of LDPC codes for power constrained systems. Another prime objective is to design a high throughput decoder architecture which is capable of supporting multiple rates and variable code lengths within minimal area.
This work aims to address and provide solutions to the above problems. As a solution to the performance estimation problem of LDPC codes, a highly efficient and novel fast BER simulation technique is developed. At the algorithm level, a performance improvement and error floor avoidance method is introduced, and a computationally efficient algorithm is developed for the sum-product decoding of LDPC codes. And finally, at the architecture level, a high throughput multi-rate variable code length implementation is presented which, when implemented, efficiently minimizes device resources while alleviating the routing complexity of the decoder.