Low-Density Parity-Check (LDPC) codes are error correcting codes with good performance in communications systems. LDPC codes, however, have heavy computational complexity. In this paper, we find out how many iterations are required for sufficient performance of LDPC codes. The Additive White Gaussian Noise (AWGN) channel model and a log-domain Sum-Product (SP) algorithm are used. Experiments measure Bit Error Rate (BER) at each iteration in given SNRs. The result of performance evaluation, the best performance is showed when the number of iteration is 25 at 5 ㏈.
Low-Density Parity-Check (LDPC) codes are error correcting codes with good performance in communications systems. LDPC codes, however, have heavy computational complexity. In this paper, we find out how many iterations are required for sufficient performance of LDPC codes. The Additive White Gaussian Noise (AWGN) channel model and a log-domain Sum-Product (SP) algorithm are used. Experiments measure Bit Error Rate (BER) at each iteration in given SNRs. The result of performance evaluation, the best performance is showed when the number of iteration is 25 at 5 ㏈.
Low-density parity-check code (LDPC) not only has good performance approaching the Shannon limit, but also has low decoding complexity and flexible structure. It is a research hot-spot in the field of channel coding in recent years and has a wide range of application prospects in optical communication systems. In this paper, the decoding aspects and performance of LDPC codes are analyzed and compared according to the bit error rate (BER) of LDPC codes. The computer simulation was carried out under additive white Gaussian noise (AWGN) channel and binary phase shift keying (BPSK) modulation. Through theoretical analysis and simulation results, this paper explores the way of multi-rate LDPC decoding.
Low-density parity-check (LDPC) codes are a subclass of linear block codes. These codes have parity-check matrices in which the ratio of the non-zero elements to all elements is low. This property is exploited in defining low complexity decoding algorithms. Low-density parity-check codes have good distance properties and error correction capability near Shannon limits. In this thesis, the sum-product and the bit-flip decoding algorithms for low-density parity-check codes are implemented on Intel Pentium M 1,86 GHz processor using the software called MATLAB. Simulations for the two decoding algorithms are made over additive white gaussian noise (AWGN) channel changing the code parameters like the information rate, the blocklength of the code and the column weight of the parity-check matrix. Performance comparison of the two decoding algorithms are made according to these simulation results. As expected, the sum-product algorithm, which is based on soft-decision decoding, outperforms the bit-flip algorithm, which depends on hard-decision decoding. Our simulations show that the performance of LDPC codes improves with increasing blocklength and number of iterations for both decoding algorithms. Since the sum-product algorithm has lower error-floor characteristics, increasing the number of iterations is more effective for the sum-product decoder compared to the bit-flip decoder. By having better BER performance for lower information rates, the bit-flip algorithm performs according to the expectations; however, the performance of the sum-product decoder deteriorates for information rates below 0.5 instead of improving. By irregular construction of LDPC codes, a performance improvement is observed especially for low SNR values.
Low-Density Parity-Check (LDPC) codes have been widely used in modern communication standards due to their strong error correction capabilities. This paper presents an experimental evaluation of a (1200, 600) irregular LDPC code over an additive white Gaussian noise (AWGN) channel, systematically comparing three decoding algorithms (Sum-Product, Normalized Min-Sum, and Offset Min-Sum) with three scheduling methods (Flooding, Layered Belief Propagation, and Residual Belief Propagation). Parameter sweeps are performed to determine the optimal normalization factor (α) for the Normalized Min-Sum and the offset factor (β) for the Offset Min-Sum. A comparative analysis is then performed on the frame error rate (FER) and convergence behavior of each algorithm and scheduling configuration, considering the maximum number of iterations set at 10 and 25. The results show that the Offset Min-Sum algorithm withβ=0.5and Layered Belief Propagation scheduling provides an acceptable trade-off between complexity and error-correction performance, closely matching the Sum-Product algorithm but at a lower computational cost. Although Residual Belief Propagation converges quickly at lower signal-to-noise ratios, it exhibits a high error floor. These findings provide practical guidelines for selecting optimal decoding configurations in resource-constrained applications.
After the introduction of iterative coding, Low Density Parity Check (LDPC) codes have received a lot of attention due to their remarkable near Shannon-limit performance and practical decoder implementation. However, when employing an LDPC code for various applications, multiple issues do arise at the simulation, algorithm and implementation levels. The first issue is the performance evaluation of the iterative LDPC decoder in the very low Bit Error Rate (BER) regions. So far, no analytical tool has been developed to evaluate the performance of LDPC codes. Unfortunately standard Monte Carlo (MC) simulations cannot be used for performance estimation in these low BER regions due to prohibitive execution times. The second issue is the efficiency of the decoding algorithm. Due to the presence of short cycles in the bipartite graph, sum-product decoding algorithms lead to considerable performance loss for short block-length LDPC codes and produce error floors for longer codes. In addition, the iterative processing and estimation of soft probabilistic values with these algorithms result in very high computational complexity, which in turn impedes the adoption of LDPC codes for power constrained systems. Another prime objective is to design a high throughput decoder architecture which is capable of supporting multiple rates and variable code lengths within minimal area.
This work aims to address and provide solutions to the above problems. As a solution to the performance estimation problem of LDPC codes, a highly efficient and novel fast BER simulation technique is developed. At the algorithm level, a performance improvement and error floor avoidance method is introduced, and a computationally efficient algorithm is developed for the sum-product decoding of LDPC codes. And finally, at the architecture level, a high throughput multi-rate variable code length implementation is presented which, when implemented, efficiently minimizes device resources while alleviating the routing complexity of the decoder.
Channel coding technique is a fundamental building block in any modern communication system to realize reliable, fast, and secure data transmission. At the same time, it is a challenging and crucial task, as the data transmission happens in a channel where noise, fading, and other impairments are present. The Low-Density Parity-Check (LDPC) codes give substantial results close to the Shannon limit when the complexity and processing delay time are unlimited. In this paper, the performance of the LDPC decoding with four algorithms was investigated. The investigated four algorithms were Belief Propagation (BP), Layered Belief Propagation (LBP), Normalized min-sum (NMS), and Offset min-sum (OMS). These algorithms were examined for code rates ranging from 1/3 to 9/10 and message block lengths (64, 512, 1024, and 5120) bits. The simulation results revealed the flexibility of these decoders in supporting these code rates and block lengths, which enables their usage in a wide range of applications and scenarios for fifth-generation (5G) wireless communication. In addition, the effect of the maximum number of decoding iterations on the error correction performance was investigated, and a gain of 5.6 dB can be obtained by using 32 decoding iterations at BER=2*10-3 instead of one decoding iteration. The results showed that the decoders performed better for longer message blocks than for short message blocks, and less power was required for transmitting longer messages. Finally, the comparison results of their performance in terms of bit error rate (BER) under the same conditions showed a gain of 0.8 dB using LBP at BER= 10-5 compared with the NMS decoding algorithm.
Low-density parity check (LDPC) codes with their near-Shannon capacity limit error correcting performance and iterative decoding algorithm are being evaluated for digital communications applications. For LDPC codes to be used in real systems, their error floors need to be investigated. In this paper, we evaluate the performance of disjoint difference set (DDS)-based LDPC codes (with column weights 3, 4, 5) and array code-based LDPC codes (with column weights 3, 4, 5) in the additive white Gaussian noise (AWGN) channel using a high-speed field programmable gate array (FPGA) simulation platform. The error floor regions (bit error rates down to 10/sup -12/) of those codes are presented. For better performance of array codes, a girth optimization method is proposed and the FPGA evaluation results are presented.