IEICE Technical Report; IEICE Tech. Rep.

Functional Demonstration of an SFQ/CMOS Hybrid Memory System

Tokuda Masamichi, 卓哉冨田, Fujiwara Kan, Hidemitsu Kojima, Yoshikawa Nobuyuki

Published Jul 8, 2004• 0 citations

Related papers

Demonstration of an SFQ/CMOS hybrid memory system using a one-instruction-set SFQ microprocessor

Yuki Hironaka, Yuki Yamanashi, Yoshikawa Nobuyuki

Design and evaluation of superconducting nanostructured transistors for SFQ-CMOS hybrid memory

Sano Kyosuke, Kohei Maruyama, Tanaka Masamitsu +3 more

Access Time Measurement of 64 kb Josephson/CMOS Hybrid Memories using SFQ Time-to-Digital Converter

Okamoto Yuji, Park Heejoung, Hyunjoo Jin +3 more

Examination of Cryogenic CMOS Amplifiers for Josephson-CMOS Hybrid Memories

Hyunjoo Jin, 啓太桑原, Yuki Yamanashi +1 more

Implementation and low speed test of ultra-fast interface circuits for Josephson-CMOS hybrid memories

K. Fujiwara, H Miyakawa, Nobuyuki Yoshikawa +3 more

Design and demonstration of high-functionality logic cells for miniaturization of SFQ switches

T. Nakagawa, Y. Hashimoto, Y. Kameda +2 more