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Proceedings of the Society Conference of IEICE

Design of Synchronous Registers and an ALU toward Single Flux Quantum Processors

Masamitsu Tanaka, Toshiaki Kondo, A. Sekiya, Akira Fujimaki, Hisao Hayakawa, 二葉子 松崎, Nobuyuki Yoshikawa

Published Aug 20, 2002• 0 citations
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We have designed a pipelined 8-bit-serial single-flux-quantum microprocessor with multiple ALUs, called CORE1 β. In the CORE1 β, two ALUs connected in cascade enable us to perform two calculations on serial data using a register-to-register instruction, to enhance the peak performance. In addition, we have introduced pipelining to boost the performance. Although the pipelining is a difficult technique that requires a complex design in the datapath, we have implemented a simplified pipeline with seven stages by using two techniques. One is the separation of clock signals for pipelining and bit processing, and the other is the introduction of new buffers driven by independent clock signals for reading and writing flexibly in order to ease the difficulty in timing design between the register file and the ALUs. According to the logic simulation, the peak performance of the designed microprocessor is estimated to be 1500 million operations per second with a power consumption of 3.3 mW. We have fabricated the CORE1 β chip by using the NEC 2.5 kA cm −2 niobium standard process, and confirmed the correct operations of several instructions using high-speed clocks.
We describe the design and implementation of a single-chip microprocessor based on LTS Rapid Single-Flux-Quantum (RSFQ) technology. Two such chips are to be used in a dual-processor module, being developed by a SUNY-TRW collaboration as a spin-off of the HTMT project. Each FLUX chip represents a simple 16-bit 2-way long-instruction-word (LIW) microprocessor with a pipelined instruction memory of 30-bit instructions, decode and issue units, 8 integer ALUs interlaced with 8 registers, and input/output ports through which two FLUX chips can communicate with each other at a 7-GHz communication rate over a multi-layer MCM. The FLUX instruction set consists of /spl sim/25 instructions. High performance is reached with a scalable design featuring (1) a very high clock rate, (2) localized, regular and ultrapipelined processing in registers with very short wires, (3) instruction-level parallelism utilization with bit-level resolution of data hazards. A 16-bit implementation of FLUX processor consists of /spl sim/90,000 Josephson junctions on a /spl sim/10 mm/spl times/15 mm chip area. Our estimates show that the processor will be able to operate at clock frequencies up to 20 GHz when implemented using TRW's 4 kA/cm/sup 2/, 1.75-/spl mu/m Nb-trilayer technology.