© 2026 Aqora Quantum S.A.S.

Terms Privacy Legal Notice

IEEE Transactions on Applied Superconductivity

FLUX chip: design of a 20-GHz 16-bit ultrapipelined RSFQ processor prototype based on 1.75-μm LTS technology

M. Dorojevets, P. Bunyk, Dmitry Y. Zinoviev

Published Mar 1, 2001• 112 citations

Abstract

We describe the design and implementation of a single-chip microprocessor based on LTS Rapid Single-Flux-Quantum (RSFQ) technology. Two such chips are to be used in a dual-processor module, being developed by a SUNY-TRW collaboration as a spin-off of the HTMT project. Each FLUX chip represents a simple 16-bit 2-way long-instruction-word (LIW) microprocessor with a pipelined instruction memory of 30-bit instructions, decode and issue units, 8 integer ALUs interlaced with 8 registers, and input/output ports through which two FLUX chips can communicate with each other at a 7-GHz communication rate over a multi-layer MCM. The FLUX instruction set consists of /spl sim/25 instructions. High performance is reached with a scalable design featuring (1) a very high clock rate, (2) localized, regular and ultrapipelined processing in registers with very short wires, (3) instruction-level parallelism utilization with bit-level resolution of data hazards. A 16-bit implementation of FLUX processor consists of /spl sim/90,000 Josephson junctions on a /spl sim/10 mm/spl times/15 mm chip area. Our estimates show that the processor will be able to operate at clock frequencies up to 20 GHz when implemented using TRW's 4 kA/cm/sup 2/, 1.75-/spl mu/m Nb-trilayer technology.

DOI: 10.1109/77.919349

Related papers

ARCHITECTURE AND DESIGN OF AN 8-BIT FLUX-1 SUPERCONDUCTOR RSFQ MICROPROCESSOR

M. Dorojevets

The first single-chip superconductor FLUX-1 microprocessor has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using 4 kA/cm2, 1.75-μm Nb/AlOx/Nb Josephson junction technology as a result of the collaboration between SUNY Stony Brook and TRW, Inc. A FLUX-1 chip represents an 8-bit deeply pipelined microprocessor prototype with a target clock frequency of 17-20 GHz. A new parallel partitioned architecture has been developed in order to tolerate interconnect delays and fill long FLUX-1 processor pipelines with useful instructions. The processor includes the 16 × 32-bit pipelined instruction memory, 8 integer arithmetic-logic units interleaved with 8 registers, the branch unit, and I/O ports for 5-GHz chip-to-chip communication over Nb microstrip lines on a chip carrier. The FLUX-1 instruction set consists of ~25 arithmetic, logical, and control instructions. A FLUX-1 microprocessor chip contains 65,759 Josephson junctions on a 10.6 mm × 13.2 mm die with flip-chip packaging. First FLUX-1 chips fabricated in August 2001 are currently under testing at TRW, Inc.

International Journal of High Speed Electronics and Systems•Jun 1, 2002•8 citations

A 20-GHz FLUX-1 superconductor RSFQ microprocessor

M. Dorojevets

The first single-chip superconductor FLUX-1 microprocessor prototype with a target clock frequency of 17-20 GHz has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using low-temperature 4 kA/cm 2 , 1.75-μm Nb/AlOx/Nb Josephson junction technology. A FLUX-1 chip represents an 8-bit deeply pipelined microprocessor with a new parallel partitioned architecture that has been developed to tolerate interconnect delays and fill long FLUX-1 pipelines with operations. A FLUX-1 chip contains 65,759 Josephson junctions on a 10.6 mm x 13.2 mm die with flip-chip packaging. First FLUX-1 chips fabricated in 2001 are currently under testing at TRW.

Journal de Physique IV (Proceedings)•May 1, 2002•4 citations

Architectural and implementation challenges in designing high-performance RSFQ processors: A FLUX-1 microprocessor and beyond

M. Dorojevets, P. Bunyk

This paper discusses the major challenges and solutions in designing high-performance superconductor processors in the context of the on-going collaboration between SUNY Stony Brook, TRW, and the JPL (NASA). It presents the architecture and organization of the first 8-bit FLUX-1 RSFQ microprocessor with a target clock frequency of 20 GHz fabricated in TRW's 4 kA/cm/sup 2/, 1.75-/spl mu/m Josephson junction technology in 2001-2002. A new parallel partitioned architecture has been developed for FLUX-1 in order to fill its long processing pipelines with operations, and reduce interconnect delays. The latest version of FLUX-1, called FLUX-1R, with improved circuit design characteristics and decreased power dissipation was fabricated in July 2002. FLUX-1R contains 63,107 Josephson junctions on a 10.35 mm /spl times/10.65 mm die with flip-chip packaging. The chip is currently under testing at TRW.

IEEE Transactions on Applied Superconductivity•Jun 1, 2003•26 citations

A 20-GHz FLUX-1 superconductor RSFQ microprocessor

M. Dorojevets

The first single-chip superconductor FLUX-1 microprocessor prototype with a target clock frequency of 17-20 GHz has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using low- temperature 4 kA/cm', 1.75-pm Nb/AlOx/Nb Josephson junction technology. A FLUX-1 chip represents an %bit deeply pipelined microprocessor with a new parallel partitioned architecture that has been developed to tolerate interconnect delays and fill long FLUX-1 pipelines with operations. A FLUX-1 chip contains 65,759 Josephson junctions on a 10.6 mm x 13.2 mm die with flip-chip packaging. First FLUX-I chips fabricated in 2001 are currently under testing at TRW.

IEEE Workshop on Low Temperature Electronics (WOLTE)•Jan 1, 2002•4 citations

Design of an 8-bit Bit-Parallel RSFQ Microprocessor

Pei-Yao Qu, Guang-Ming Tang, Jia-Hong Yang +4 more

With Moore's law approaching its physical limits, low-temperature computing technology is ushering in unprecedented development opportunities. Rapid single-flux-quantum (RSFQ) circuit technology is currently the most mature superconducting integrated circuit technology. Based on the current fabrication process, we propose an 8-bit bit-parallel RSFQ microprocessor. The proposed microprocessor processes 8-bit data each clock cycle. Ten different instructions are executed. The microprocessor mainly consists of an on-chip instruction memory, two data registers, an instruction decoder, an 8-bit bit-parallel arithmetic logic unit, and a program counter. The microprocessor contains 7702 JJs (based on the Open Dataset of CONNECT Cell Library for AIST ADP2) without considering splitters, Josephson transmission lines, and passive transmission lines. We perform a logic-level simulation of the proposed microprocessor. The simulation results show correct operation with a target frequency of 16.7 GHz.

IEEE Transactions on Applied Superconductivity•Aug 18, 2020•12 citations

High-Speed Operation of Random-Access-Memory-Embedded Microprocessor With Minimal Instruction Set Architecture Based on Rapid Single-Flux-Quantum Logic

Ryo Sato, Yuki Hatanaka, Yuki Ando +4 more

We present design and experimental results of a rapid single-flux-quantum (RSFQ) bit-serial microprocessor with reduced-size embedded random access memories (RAMs) and with a minimal instruction set, called CORE e2h. The microprocessors called CORE e series have been developed for demonstrating small-scale program execution, such as loop calculation and sorting, in order to show the first prototype of a stored-program computer using the RSFQ technology. The CORE e2h is the most simplified variation of the CORE e series, which is equipped with only two registers, and can execute 13 instructions. The target clock frequency for bit-serial operation is 50 GHz, while the designed system clock cycle is 2 GHz. We carefully designed every component, implementing functionality using a small number of Josephson junctions with a small footprint. We fabricated several chips of the CORE e2h microprocessor integrated with two 128-bit shift-register-based RAMs on the same die. We experimentally obtained correct operations for all the instructions, and confirmed high-speed transfer between the instruction memory and controller unit and between the data memory and datapath at around 50 GHz.

IEEE Transactions on Applied Superconductivity•Dec 20, 2016•63 citations

We describe the design and implementation of a single-chip microprocessor based on LTS Rapid Single-Flux-Quantum (RSFQ) technology. Two such chips are to be used in a dual-processor module, being developed by a SUNY-TRW collaboration as a spin-off of the HTMT project. Each FLUX chip represents a simple 16-bit 2-way long-instruction-word (LIW) microprocessor with a pipelined instruction memory of 30-bit instructions, decode and issue units, 8 integer ALUs interlaced with 8 registers, and input/output ports through which two FLUX chips can communicate with each other at a 7-GHz communication rate over a multi-layer MCM. The FLUX instruction set consists of /spl sim/25 instructions. High performance is reached with a scalable design featuring (1) a very high clock rate, (2) localized, regular and ultrapipelined processing in registers with very short wires, (3) instruction-level parallelism utilization with bit-level resolution of data hazards. A 16-bit implementation of FLUX processor consists of /spl sim/90,000 Josephson junctions on a /spl sim/10 mm/spl times/15 mm chip area. Our estimates show that the processor will be able to operate at clock frequencies up to 20 GHz when implemented using TRW's 4 kA/cm/sup 2/, 1.75-/spl mu/m Nb-trilayer technology.

The first single-chip superconductor FLUX-1 microprocessor has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using 4 kA/cm2, 1.75-μm Nb/AlOx/Nb Josephson junction technology as a result of the collaboration between SUNY Stony Brook and TRW, Inc. A FLUX-1 chip represents an 8-bit deeply pipelined microprocessor prototype with a target clock frequency of 17-20 GHz. A new parallel partitioned architecture has been developed in order to tolerate interconnect delays and fill long FLUX-1 processor pipelines with useful instructions. The processor includes the 16 × 32-bit pipelined instruction memory, 8 integer arithmetic-logic units interleaved with 8 registers, the branch unit, and I/O ports for 5-GHz chip-to-chip communication over Nb microstrip lines on a chip carrier. The FLUX-1 instruction set consists of ~25 arithmetic, logical, and control instructions. A FLUX-1 microprocessor chip contains 65,759 Josephson junctions on a 10.6 mm × 13.2 mm die with flip-chip packaging. First FLUX-1 chips fabricated in August 2001 are currently under testing at TRW, Inc.

The first single-chip superconductor FLUX-1 microprocessor prototype with a target clock frequency of 17-20 GHz has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using low-temperature 4 kA/cm 2 , 1.75-μm Nb/AlOx/Nb Josephson junction technology. A FLUX-1 chip represents an 8-bit deeply pipelined microprocessor with a new parallel partitioned architecture that has been developed to tolerate interconnect delays and fill long FLUX-1 pipelines with operations. A FLUX-1 chip contains 65,759 Josephson junctions on a 10.6 mm x 13.2 mm die with flip-chip packaging. First FLUX-1 chips fabricated in 2001 are currently under testing at TRW.

This paper discusses the major challenges and solutions in designing high-performance superconductor processors in the context of the on-going collaboration between SUNY Stony Brook, TRW, and the JPL (NASA). It presents the architecture and organization of the first 8-bit FLUX-1 RSFQ microprocessor with a target clock frequency of 20 GHz fabricated in TRW's 4 kA/cm/sup 2/, 1.75-/spl mu/m Josephson junction technology in 2001-2002. A new parallel partitioned architecture has been developed for FLUX-1 in order to fill its long processing pipelines with operations, and reduce interconnect delays. The latest version of FLUX-1, called FLUX-1R, with improved circuit design characteristics and decreased power dissipation was fabricated in July 2002. FLUX-1R contains 63,107 Josephson junctions on a 10.35 mm /spl times/10.65 mm die with flip-chip packaging. The chip is currently under testing at TRW.

The first single-chip superconductor FLUX-1 microprocessor prototype with a target clock frequency of 17-20 GHz has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using low- temperature 4 kA/cm', 1.75-pm Nb/AlOx/Nb Josephson junction technology. A FLUX-1 chip represents an %bit deeply pipelined microprocessor with a new parallel partitioned architecture that has been developed to tolerate interconnect delays and fill long FLUX-1 pipelines with operations. A FLUX-1 chip contains 65,759 Josephson junctions on a 10.6 mm x 13.2 mm die with flip-chip packaging. First FLUX-I chips fabricated in 2001 are currently under testing at TRW.

With Moore's law approaching its physical limits, low-temperature computing technology is ushering in unprecedented development opportunities. Rapid single-flux-quantum (RSFQ) circuit technology is currently the most mature superconducting integrated circuit technology. Based on the current fabrication process, we propose an 8-bit bit-parallel RSFQ microprocessor. The proposed microprocessor processes 8-bit data each clock cycle. Ten different instructions are executed. The microprocessor mainly consists of an on-chip instruction memory, two data registers, an instruction decoder, an 8-bit bit-parallel arithmetic logic unit, and a program counter. The microprocessor contains 7702 JJs (based on the Open Dataset of CONNECT Cell Library for AIST ADP2) without considering splitters, Josephson transmission lines, and passive transmission lines. We perform a logic-level simulation of the proposed microprocessor. The simulation results show correct operation with a target frequency of 16.7 GHz.

We present design and experimental results of a rapid single-flux-quantum (RSFQ) bit-serial microprocessor with reduced-size embedded random access memories (RAMs) and with a minimal instruction set, called CORE e2h. The microprocessors called CORE e series have been developed for demonstrating small-scale program execution, such as loop calculation and sorting, in order to show the first prototype of a stored-program computer using the RSFQ technology. The CORE e2h is the most simplified variation of the CORE e series, which is equipped with only two registers, and can execute 13 instructions. The target clock frequency for bit-serial operation is 50 GHz, while the designed system clock cycle is 2 GHz. We carefully designed every component, implementing functionality using a small number of Josephson junctions with a small footprint. We fabricated several chips of the CORE e2h microprocessor integrated with two 128-bit shift-register-based RAMs on the same die. We experimentally obtained correct operations for all the instructions, and confirmed high-speed transfer between the instruction memory and controller unit and between the data memory and datapath at around 50 GHz.