Superconductor electronics holds records for clock frequency and energy efficiency at the chip level, and is also projected to large systems that can absorb the cooling overhead. These advantages have nevertheless only managed to give this technology a back seat to CMOS digital circuits, which offer orders of magnitude more complexity. Furthermore, pursuing the CMOS paradigm with superconductor circuits would bring their clock frequency down to that of CMOS circuits. This makes superconductor technology much more open to risky innovations and even for paradigm changes. In the paper we point out that both (speed and energy efficiency) advantages of superconductor electronics could be preserved due to a unique composition of memory and logic functions of RSFQ cells. We propose to reorganize the original RSFQ cells into a new family of Memory And loGIC (MAGIC) gate/register objects that run arithmetic calculations as well as store results. The new MAGIC objects eliminate the time and energy overheads associated with the conventional transfer of computed data to memory by essentially reducing the transfer distance to zero. The new objects could serve as building blocks for distributed MAGIC-compatible architectures, differing from CMOS-like register files by processing as well as storing data. A simple Logic Unit (LU) would be sufficient to control the MAGIC registers, because the registers would provide most of the arithmetic functions and separate ALUs would not be needed. The reduction of the data exchange between logic and memory units leads to additional energy saving. Factorization of large integers is presented as an example illustrating the speed and density advantages of the new approach. The end result will be a superior technology which offers a combination of performance and energy efficiency unattainable by existing technologies or their possible extensions.
Superconductor electronics holds records for clock frequency and energy efficiency at the chip level, and is also projected to large systems that can absorb the cooling overhead. These advantages have nevertheless only managed to give this technology a back seat to CMOS digital circuits, which offer orders of magnitude more complexity. Furthermore, pursuing the CMOS paradigm with superconductor circuits would bring their clock frequency down to that of CMOS circuits. This makes superconductor technology much more open to risky innovations and even for paradigm changes. In the paper we point out that both (speed and energy efficiency) advantages of superconductor electronics could be preserved due to a unique composition of memory and logic functions of RSFQ cells. We propose to reorganize the original RSFQ cells into a new family of Memory And loGIC (MAGIC) gate/register objects that run arithmetic calculations as well as store results. The new MAGIC objects eliminate the time and energy overheads associated with the conventional transfer of computed data to memory by essentially reducing the transfer distance to zero. The new objects could serve as building blocks for distributed MAGIC-compatible architectures, differing from CMOS-like register files by processing as well as storing data. A simple Logic Unit (LU) would be sufficient to control the MAGIC registers, because the registers would provide most of the arithmetic functions and separate ALUs would not be needed. The reduction of the data exchange between logic and memory units leads to additional energy saving. Factorization of large integers is presented as an example illustrating the speed and density advantages of the new approach. The end result will be a superior technology which offers a combination of performance and energy efficiency unattainable by existing technologies or their possible extensions.
The finite speed of light sets a fundamental limitation for the time required to communicate between any remote memory and logic devices. This limitation alone implies that the latency of communication cycles between, say, 1-cm processor and memory chips is longer than 120 ps. To bypass this limitation, we propose a novel way of using SFQ cells and devices that eliminates the communication delays by storing and processing information in the same location. We introduce new objects (cells and devices) that store one of input operands, process it during a logic operation that might involve other operands, and replace the initially stored operand by the result of the logic operation. Because these objects execute both Memory And loGIC functions we nicknamed them MAGIC cells and devices. Physically each MAGIC object is either a single flip-flop or composed of flip-flops. MAGIC objects are compatible with, or even may constitute a part of, RSFQ technology. We discuss functional devices built of MAGIC cells. These devices are potentially faster, smaller in size, and have modest requirements for external memory. This is because the suggested functional circuits partly self-satisfy storage needs by utilizing their inherent ability for storing data.
Abstract Superconductor Electronics (SCE) is a fast and power-efficient technology with great potential for overcoming conventional CMOS electronics’ scaling limits. Nevertheless, the primary challenge confronting SCE today is its integration level, which lags several orders of magnitude behind CMOS circuits. In this study, we have innovated and simulated a novel logic family grounded in the principles of phase shifts occurring in 0 and π Josephson junctions. The fast phase logic (FPL) eliminates the need for large inductor loops and shunt resistances by combining the half-flux and phase logic. Therefore, the Josephson junction (JJ) area only limits the integration density. The cells designed with this paradigm are fast, and the clock-to-Q delay for logic cells is about 4ps. While maintaining over 50% parameter margins for wiring cells. This logic is power efficient and can increase the integration by at least 100×in the SCE chips.
New superconductor single flux quantum logics with no static power dissipation in bias resistors, such as Reciprocal Quantum Logic (RQL), offer opportunities to create energy-efficient superconductor processors operating at high frequencies with ultra-low power consumption. This paper discusses the results of our work on the cell-level design and analysis of a benchmark set of 32-/64-bit RQL processor integer and floating-point units such as adders, multipliers, an arithmetic-logic unit, and an array shifter, as well as small 1-4 Kbit RQL on-chip storage components such as register files, on-chip memory, and the top level caches. Our layout-aware design process includes the complete cell-level design and approximate physical layout of the circuits followed by the VHDL simulation, verification, and energy profiling using our RQL VHDL cell library tuned to the future MIT Lincoln Laboratory 10 kA/cm2 248 nm process with 10 Nb metal layers and the minimum JJ critical current of 38 μA. Our designs have the energy efficiency of ~1.0 single-precision TFLOPS/W and '0.5 double-precision TFLOPS/W for floating-point units, and ~1-24 TOPS/W for 32-bit integer units at room temperature using the cryocooling efficiency of 0.1 % (1000 W/W). The 1-4 Kbit 32-/64-bit multi-ported scratchpad memory, register files, write-through and write-back caches designed with RQL Non-Destructive Read-Out storage cells have the average energy consumption of 3.0-9.5 fJ/bit/operation at room temperature using the cryocooling efficiency of 0.1%. While these results are very promising, more work is needed to evaluate the contribution of the energy costs of instruction scheduling and off-chip main memory access to the energy efficiency of RQL computing across a whole system.
Superconductor digital technology based on Rapid Single Flux Quantum logic (RSFQ) offers more than 50 times gain in speed and more than 100 reduction in power consumption over mainstream CMOS devices. However, the necessity of cooling down to 4 K and modest degree of integration density currently available mean that employing RSFQ is reasonable only for the tasks that are impossible or ineffective to implement in CMOS technology. One of the promising applications of the RSFQ technology is Digital Signal Processing (DSP) for telecommunications. Interference cancellation is a bottleneck for all existing systems in terms of the performance gain that is theoretically possible and technically realizable using conventional technology. The crucial factor is computational complexity required to handle multiple access interference. The general approach is to compute the interference using available data about propagation channels and then either remove it from received signal or use to predistort the transmitted signal. Computation of the interference matrix can easily fall into 100 Gops range, furthermore, the most e±cient algorithms are based on successive iterations. This requires not only high overall performance of the DSP but also high actual clock rate.This thesis reports a proposed architecture of an RSFQ Successive Interference Canceller and a design of an RSFQ Digital Signal Processor based on hybrid RSFQ-CMOS memory suitable for a general matrix on matrix multiplication algorithm. The processor consists of an RSFQ Multiply-Accumulate Unit, memory caches and a synchronization block, partitioned into multiple chips, and a large CMOS memory.The complexity of the RSFQ DSP is 10x10 multiplication, rounding to 14 bits, 18 bits accumulator length and 3.7 Kb memory cache. In order to implement the RSFQ DSP, we have developed approach to simulate and describe the RSFQ circuits using VHDL. The maximum simulated clock frequency is equal to 24 GHz for Hypres 4.5 kA/cm2 process and optimum communication bandwidth with CMOS memory is 2 Gbps.Components of the processor such as 4x4 two's complement and 5x5 parallel multipliers, 4x5, 20x5 and 4x15 parallel shift registers, a 5-bit serial adder have been designed and experimentally tested. The simplified version of the RSFQ DSP consisting of a 4x4 MAC with rounding to 5 bits and 17x6 memory caches has been designed for Hypres 4.5 kA/cm2 process and fabricated.
Superconducting logic circuits based on Josephson junctions (JJ) are the fastest, lowest power solid state digital circuit technology known. Large scale integration of such circuits has also been demonstrated. By contrast, current superconducting memory circuits based on flux quantization are not equivalently advanced. Very dense memory chips have not been possible to date and seem unlikely to come without new invention. The goal of this project was to explore alternative approaches to memory that would be compatible with Josephson junction logic circuits and capable of much denser memory arrays. Five new approaches were investigated ranging from modification to the current approach, use of semiconductor CMOS and wholly new concepts based on new physical principles. Three of these were identified as worth pursuing. They are use of cooled CMOS, use of cryogenic hybrid JJ/CMOS memory concepts and a totally new magnetoresistive approach to memory based on the superconductor/ferromagnet proximity effect.
The rapid-pace growing demand for high-performance computation and big-data manipulation entails substantial increase in global power consumption, and challenging thermal management. Thus, there is a need in allocating competitive alternatives for complementary metal-oxide-semiconductor (CMOS) technologies. Superconducting platforms, such as rapid single flux quantum (RSFQ) lack electric resistance and excel in power efficiency and time performance. However, traditional RSFQs require 3D geometry for their Josephson junctions (JJs) imposing a large footprint, and hence preventing device miniaturization and increasing processing time. Here, we demonstrate that RSFQ logic circuits of planar geometry with weak-link bridges are scalable, relatively easy to process and are CMOS-compatible on a Si chip. Universal logic gates, as well as combinational arithmetic circuiting that are based on these devices are demonstrated. The power consumption and processing time of these logic circuits were as low as 0.8 nW and 13 ps, an order of magnitude improvement with respect to the equivalent traditional-RSFQ logic circuits and two orders of magnitude with respect to CMOS. The competitive performance of planar RSFQ logic circuits renders them for promising CMOS substitutes, especially in the supercomputational realm.