Superconducting logic circuits based on Josephson junctions (JJ) are the fastest, lowest power solid state digital circuit technology known. Large scale integration of such circuits has also been demonstrated. By contrast, current superconducting memory circuits based on flux quantization are not equivalently advanced. Very dense memory chips have not been possible to date and seem unlikely to come without new invention. The goal of this project was to explore alternative approaches to memory that would be compatible with Josephson junction logic circuits and capable of much denser memory arrays. Five new approaches were investigated ranging from modification to the current approach, use of semiconductor CMOS and wholly new concepts based on new physical principles. Three of these were identified as worth pursuing. They are use of cooled CMOS, use of cryogenic hybrid JJ/CMOS memory concepts and a totally new magnetoresistive approach to memory based on the superconductor/ferromagnet proximity effect.
Superconducting logic circuits based on Josephson junctions (JJ) are the fastest, lowest power solid state digital circuit technology known. Large scale integration of such circuits has also been demonstrated. By contrast, current superconducting memory circuits based on flux quantization are not equivalently advanced. Very dense memory chips have not been possible to date and seem unlikely to come without new invention. The goal of this project was to explore alternative approaches to memory that would be compatible with Josephson junction logic circuits and capable of much denser memory arrays. Five new approaches were investigated ranging from modification to the current approach, use of semiconductor CMOS and wholly new concepts based on new physical principles. Three of these were identified as worth pursuing. They are use of cooled CMOS, use of cryogenic hybrid JJ/CMOS memory concepts and a totally new magnetoresistive approach to memory based on the superconductor/ferromagnet proximity effect.
The goal of this program is to explore advanced alternatives to the standard approaches to memory in Josephson junction digital electronics. The work includes the physics, circuits and systems aspects of the problem. It is widely recognized that memory is the weak suit of digital superconductive electronics. There are several problems. They are hard to build, particularly at high densities. Their speed is being challenged by leading edge semiconductor memories, albeit at the expense of high power dissipation. They are susceptible to trapped flux, which is both random in space and likely varying in time. All the current approaches to memory are based on the concept of storage of magnetic flux in a superconducting ring first proposed over 25 years ago by Anacker. Basically, there have been no new ideas in superconductive memory since that time.
The lack of dense, fast, energy efficient memory has been the main detractor for multiple superconducting digital projects in the past. Recently, fundamental physics research in superconductor-ferromagnet thin-film tunnel structures created a new opportunity to solve this long-standing problem. Superconductivity and ferromagnetism, two deeply antagonistic electronic properties, can co-exist in form of Magnetic Josephson Junctions (MJJs). The superconducting-ferromagnetic MJJs are electrically compatible with traditional superconductor-insulator-superconductor (SIS) Josephson junctions (JJs) used for digital energy-efficient single flux quantum (eSFQ/ERSFQ) circuits. Both MJJ and JJ circuits have similar fabrication process and can be integrated on a single chip. As a result, a combination of MJJs and JJs can be used to form addressable memory cells, energy-efficient memory periphery circuits and programmable logic elements. In this paper, we present the test results of superconductor-insulator-ferromagnet-superconductor (SIFS) MJJs showing their applicability for superconducting spintronic memory and digital circuits.
Abstract : Lack of high-density, fast and memory has been a long-standing problem in superconducting digital electronics. Alternative Josephson-junction-based memory cells and peripheral circuits have intrinsic problems which impede the application of that kind of memory. The CMOS-Josephson hybrid memory idea was proposed in 1992 to circumvent this problem. In the present work we have designed and demonstrated a 64-kb CMOS-Josephson hybrid memory working at 1 GHz. In order to make the hybrid idea practical, a complete and comprehensive 4 K short-channel CMOS model for digital circuits was developed for this dissertation. It has been used in the design of the memory core and peripheral circuits. A fast hybrid interface circuit that transforms single-flux-quantum millivolt 2-ps pulse signals to CMOS volt-level signals has been studied and the optimized design has been completed. Using a nonvolatile cryogenic 3-T DRAM cell, the memory core is designed in such a way that the access time is much less than for room-temperature operation, not only because of the performance upgrade due to the temperature decrease but also because of a different reading mechanism. Fabricated by commercial submicron CMOS processes (0.25 microns and 0.18 microns) and a Nb/AlOx/Nb Josephson-junction process with 2.5 kA/cm2 tunneling current density, the memory chips were bonded together by direct wire-bonding and by flip-chip bump-bonding and tested at low frequencies, high frequencies, respectively. A subnanosecond access time is obtained both from simulations and experiments. The power for an interface circuit is measured to be 0.6 mW. The memory core consumes even less power. The total power consumption depends on the operation mode of the memory and is calculated to be 10 mW for reading and 28 mW for writing. Simulations also indicate that, with more advanced semiconductor and superconductor technologies, larger and faster hybrid memories are expected to be achievable in the future.
In this paper, the author describes studies on electronic devices and circuits utilizing both of superconductors and semniconductors. First, a design of an interface circuit composed of Josephson junctions and MOSFETs is described. The Josephson-MOS interface circuit will be used for realizing high-speed data communication between a Josephson digital circuit and a semiconductor one. Second, fabrication and characterization of MOSFETs with superconductive NbN gate electrodes are described. The use of superconductive gates makes it easy to hybridize MOSFETs with Josephson junctions. Finally, studies of Josephson-CMOS hybrid memory circuits are introduced.
The last several decades have seen an explosion in the use and size of computers for scientific applications. The US Department of Energy has set an ExaScale computing goal for high performance computing that is projected to be unattainable by current CMOS computing designs [1]. This has led to a renewed interest in superconducting computing as a means of beating these projections. One of the primary requirements of this thrust is the development of an efficient cryogenic memory. Estimates of power consumption of early Rapid Single Flux Quantum (RSFQ) memory designs are on the order of MW, far too steep for any real application [1]. Therefore, other memory concepts are required. S/F/S Josephson Junctions, a class of device in which two superconductors (S) are separated by one or more ferromagnetic layers (F) has shown promise as a memory element. Several different systems have been proposed utilizing either the spin-singlet or spin-triplet superconducting states [2]. This talk will discuss the concepts underpinning these devices, and the recent work done to demonstrate their feasibility. [1] Energy-Efficient Superconducting Computing Power Budgets and Requirements, D. Scott Holmes, Andrew L. Ripple, Marc A. Manheimer, IEEE Trans. Appl. Supercon., Vol 23, No. 3, June 2013 [2] B. M. Niedzielski et al., “Use of Pd-Fe and Ni-Fe-Nb as soft magnetic layers in ferromagnetic Josephson junctions for nonvolatile cryogenic memory,” IEEE Trans. Appl. Supercond., vol. 24, no. 4, Aug. 2014, Art. ID. 1800307.
Superconducting digital pulse-conserving logic and Josephson static random access memory (JSRAM) memory together enable scalable circuits with energy efficiency 100× beyond leading-node CMOS. Circuit designs support high throughput and low latency when implemented in an advanced fabrication stack with high-critical-current-density Josephson junctions of 1000 μA/μm2. Pulse-conserving logic produces one single-flux-quantum output for each input and includes a three-input, three-output gate producing logical or3, majority3, and and3. Gate macros using dual-rail data encoding eliminate inversion latency and produce efficient implementations of all standard logic functions. A full adder using 70 Josephson junctions has a carry-out latency of 5 ps corresponding to an effective 12 levels of logic at 30 GHz. JSRAM memory uses single-flux-quantum signals throughout an active array to achieve throughput at the same clock rate as the logic. The unit cell has eight Josephson junctions, a signal propagation latency of 1 ps, and a footprint of 2 μm2. Projected density of JSRAM is 4 MB/cm2, and computational density of pulse-conserving logic is on par with leading node CMOS accounting for power densities and clock rates.