The rapid-pace growing demand for high-performance computation and big-data manipulation entails substantial increase in global power consumption, and challenging thermal management. Thus, there is a need in allocating competitive alternatives for complementary metal-oxide-semiconductor (CMOS) technologies. Superconducting platforms, such as rapid single flux quantum (RSFQ) lack electric resistance and excel in power efficiency and time performance. However, traditional RSFQs require 3D geometry for their Josephson junctions (JJs) imposing a large footprint, and hence preventing device miniaturization and increasing processing time. Here, we demonstrate that RSFQ logic circuits of planar geometry with weak-link bridges are scalable, relatively easy to process and are CMOS-compatible on a Si chip. Universal logic gates, as well as combinational arithmetic circuiting that are based on these devices are demonstrated. The power consumption and processing time of these logic circuits were as low as 0.8 nW and 13 ps, an order of magnitude improvement with respect to the equivalent traditional-RSFQ logic circuits and two orders of magnitude with respect to CMOS. The competitive performance of planar RSFQ logic circuits renders them for promising CMOS substitutes, especially in the supercomputational realm.
The rapid-pace growing demand for high-performance computation and big-data manipulation entails substantial increase in global power consumption, and challenging thermal management. Thus, there is a need in allocating competitive alternatives for complementary metal-oxide-semiconductor (CMOS) technologies. Superconducting platforms, such as rapid single flux quantum (RSFQ) lack electric resistance and excel in power efficiency and time performance. However, traditional RSFQs require 3D geometry for their Josephson junctions (JJs) imposing a large footprint, and hence preventing device miniaturization and increasing processing time. Here, we demonstrate that RSFQ logic circuits of planar geometry with weak-link bridges are scalable, relatively easy to process and are CMOS-compatible on a Si chip. Universal logic gates, as well as combinational arithmetic circuiting that are based on these devices are demonstrated. The power consumption and processing time of these logic circuits were as low as 0.8 nW and 13 ps, an order of magnitude improvement with respect to the equivalent traditional-RSFQ logic circuits and two orders of magnitude with respect to CMOS. The competitive performance of planar RSFQ logic circuits renders them for promising CMOS substitutes, especially in the supercomputational realm.
Superconductive logic based on Josephson junctions (JJ) is a promising technology for energy efficient supercomputers and cloud computing. This technology can deliver significant improvements in performance and energy efficiency as compared to CMOS. Superconductive circuits, however, suffer from low density integration as compared to CMOS, primarily due to the limited scalability of the inductors. To improve the scalability of superconductive logic, a logic family based on a novel JJ technology,$2\phi $-JJ, has been proposed that eliminates the inductors. In this brief, three circuits are presented which exploit this scalable inductor-less technology. This novel$2\phi $-JJ technology represents the data as half flux quantum (HFQ) pulses, which improves the energy efficiency and speed as compared to standard superconductive logic such as rapid single flux quantum (RSFQ). Unlike RSFQ, the proposed circuits dynamically switch upon receiving an HFQ pulse, saving energy. These$2\phi $-JJ logic circuits operate 2.25X faster and require 2.6X less energy as compared to RSFQ.
Advancement of superconductor digital electronics, especially Rapid Single Flux Quantum (RSFQ) logic circuit is described. Ultra short pulse of a voltage generated across a Josephson junction and release from charging/discharging process for signal transmission in RSFQ circuits enable us to reduce power consumption and gate delay. The power-delay products (PDPs) of RSFQ integrated circuits (ICs) are 4 or 5 orders of magnitude smaller than those of semiconductor ICs. The fabrication process technology and the related designing technology have been advanced, and RSFQ ICs have been applied to software-defined radio receivers, superconductor detector array systems, and supercomputers. Recently, several kinds of energy-efficient single flux quantum circuit have been proposed to obtain further advantage to semiconductor devices. The PDPs of these circuits become at least 1 order smaller than those of conventional RSFQ circuits.
Design and manufacturing of superconductive electronics have been evolving over the past three decades with significant progress made in related fields. Rapid single flux quantum (RSFQ) logic circuits have become popular among superconductive logic families and its energy-efficient variants (ERSFQ and eSFQ) have shown promise as an ultra lowpower and high-speed circuit fabric. SFQ circuits have been demonstrated at tens of GHz with an energy consumption of an attojoule per gate. There are many differences between SFQ and conventional CMOS circuits. SFQ logic circuits are based on the manipulation of the quantized magnetic flux pulses. Most of the logic gates are sequential in nature requiring the clock to be distributed to every logic gate. SFQ logic gates have no gain and hence splitters are needed to drive multiple fanouts. Design and successful demonstration of a controllable superconducting switch and a compact reliable memory element have evaded researchers so far. This paper starts by describing key differences between SFQ logic and conventional CMOS and concludes by listing key challenges that must be overcome to achieve the very large scale integration of SFQ circuits and make the demonstration of a superconductive CPU a reality.
The growing market for fast floating-point coprocessors, digital signal processing chips, and graphics processors has created a demand for high speed, area efficient multipliers. Current architectures range from small, low-performance shift and add multipliers, to large, high-performance array and tree multipliers. Conventional linear array multipliers achieve high performance in a regular structure, but require large amounts of silicon. Tree structures achieve even higher performance than linear arrays but the tree interconnection is more complex and less regular, making them even larger than linear arrays. Ideally, one would want the speed benefits of a tree structure, the regularity of an array multiplier, and the small size of a shift and add multiplier. In electronics, rapid single flux quantum (RSFQ) is a digital electronics technology that relies on quantum effects in superconducting devices, namely Josephson junctions, to process digital signals. Josephson junctions are the active elements for RSFQ electronics, just as transistors are the active elements for semiconductor electronics. However, RSFQ is not a quantum computing technology in the traditional sense. Even so, RSFQ is very different from the traditional CMOS transistor technology used in every day computers due to its power efficiency and high speed it is being used.
We report on a voltage-state logic family based on shunted Josephson junctions and on the Rapid Single Flux Quantum (RSFQ) concept. Storing information in a voltage-state form makes this Multi-Flux-Quantum Logic (MFQL) easier to match to complementary metal-oxide semiconductor (CMOS) circuits. The switching of MFQL element between the voltage and zero-voltage states takes a minimum of two SFQ pulses, and the switching time of this logic is comparable to that of RSFQ logic. The key logic element is an inverter in the form of an asymmetric interferometer, and the underlying idea is to use a separate superconducting wire to supply a standard dc output voltage for the elements. The asymmetric interferometer, directly coupled to the other elements, is actually a Josephson junction based three-terminal device or transistor. Elements such as NOT, OR, NOR, XOR, XNOR, a toggle flip-flop, and an RS trigger have been simulated, and show margins better than /spl plusmn/24%. The performance of this logic with current circuit fabrication technologies is also discussed.
Josephson Junction (JJ) based superconductor logic families have been proposed and implemented to process analog and digital signals [1] for its low energy dissipation and ultrafast switching speed. Thanks to its construction of resistance-less wires and ultrafast switches, it can operate at clock frequencies of several tens of gigahertz and even hundreds of thousands of times as energy efficient as its CMOS counterparts. It has been perceived to be an important candidate to replace stateof-the-art CMOS due to the superior potential in operation speed and energy efficiency, as recognized by the U.S. IARPA C3 and SuperTools Programs and Japan MEXT-JSPS Project. The design and fabrication of superconducting circuits have already been established [2]-[4]. In addition, a prototype superconducting microprocessor "Core 1" has been demonstrated in 2004 [3], which is able to execute instructions at a high clock frequency of several tens of gigahertz, and with extremely low-power dissipation. These achievements make superconducting electronics highly promising for future high-performance computing applications. As one of the most matured superconducting technology, the Rapid-Single-Flux-Quantum (RSFQ) technology is proposed by K. Likharev, O. Mukhanoc, V. Semenov in 1985 [1]. Despite its capability to be operated at an ultra-high speed of hundreds of GHz while maintaining extremely low switching energy (10^-19 J), it suffers from an increasing static power due to on-chip resistors that are required for constant DC bias supply for the main RSFQ circuit. Numerous methods have been proposed to resolve the static power dissipation problem of RSFQ, including low-voltage RSFQ (LV-RSFQ) [5], reciprocal quantum logic (RQL) [6], LRbiased RSFQ [7] and energy-efficient single-flux quantum (eSFQ) [8]. The Adiabatic Quantum-Flux-Parametron (AQFP) technology, on the other hand, uses AC bias/excitation currents as both multiphase clock signal and power supply [9] to mitigate the power consumption overhead of DC bias while operating at a frequency of few GHz. Consequently, AQFP is remarkably energy efficient compared to RSFQ, albeit operating at a lower frequency. The energy-delay-product (EDP) of the AQFP circuits fabricated using processes such as the AIST standard process 2 (STP2) and the MIT-LL SFQ process [10], [11], is at least 200 times smaller than those of the other energy-efficient superconductor logics and is only three orders of magnitude larger than the quantum limit [9]. Physical testing results of an AQFP 8-bit carry-look-ahead adder and large scale circuits consisting up-to 10,000 AQFP logic gates have demonstrated the AQFP being a promising technology that is robust against circuit parameter variations [12]. Despite the high application potential of AQFP in VLSI circuits, a systematic, automatic synthesis framework for AQFP is imminent. There are two features of AQFP that restrict conventional CMOS synthesis methods being directly applied on AQFP. In spite of And-Or-Inverter(AOI) based representation, which conventional CMOS circuits highly relies on, AQFP circuits prefer majority gates. In fact, its two inputs AND and OR gates are also built with three inputs majority gate with one input being constant. In addition, given its clock-synchronized data propagation nature, AQFP technology requires all inputs to any gate having equal delay. In order to meet this balanced timing requirement, splitters and buffers need to be inserted to the circuit. As a matter of fact, some circuit size can be doubled even with optimum amount of buffers and splitters inserted. The buffer and splitter insertion method can have a huge impact on the overall resource consumption. As the design complexity increases, an unoptimized buffer and splitter insertion method could result in huge amount of unnecessary buffers and splitters added. In addition to a complete synthesis framework, an Integrated Development Environment (IDE) for AQFP design is also lacking. It is imminent to have an IDE for AQFP integrating tools that offer schematic and layout editor, simulation and analysis for better and more efficient AQFP design flow. In this paper, we propose a complete design tool for AQFP design including an Integrated Development Environment (IDE), a complete majority based synthesis framework and a buffer and splitter insertion framework. we propose a majority gates synthesis framework for AQFP circuits that is capable of converting any AOI netlist to its corresponding MAJ netlist by mapping all feasible three-input sub-netlists to corresponding MAJ based implementations. In addition, we also propose an automated buffer and splitter insertion method that is capable of adding the optimum amount of buffers and splitters to any given gate-level netlist. The proposed method can find the minimum amount of buffers and splitters to inserted to achieve equal delay with any library limitation on the size of splitters. Experimental results suggest that the proposed methods can deliver very optimized results. The majority conversion tool can reduce circuit size by an average of 16:47% and delay by 30:21% in average. The buffer and splitter insertion tool only introduces an average of 14:24% overhead in size and 4:70% delay with splitter fanout size limited to 4 compared to an unachievable ideal results with no limitations on splitter fan-out size. Overall, the balanced design in majority gates can be reduced by 23:85% and 29:54% in size and delay compared to its AND/OR/Inverter implemented counterpart.