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IMPLEMENTATION OF POWER EFFICIENT 20- GHZ RSFQ MULTIPLIER

Srinivas Sapa, P Balanagu

Published Aug 14, 2016• 0 citations
OpenAlex

Abstract

The growing market for fast floating-point coprocessors, digital signal processing chips, and graphics processors has created a demand for high speed, area efficient multipliers. Current architectures range from small, low-performance shift and add multipliers, to large, high-performance array and tree multipliers. Conventional linear array multipliers achieve high performance in a regular structure, but require large amounts of silicon. Tree structures achieve even higher performance than linear arrays but the tree interconnection is more complex and less regular, making them even larger than linear arrays. Ideally, one would want the speed benefits of a tree structure, the regularity of an array multiplier, and the small size of a shift and add multiplier. In electronics, rapid single flux quantum (RSFQ) is a digital electronics technology that relies on quantum effects in superconducting devices, namely Josephson junctions, to process digital signals. Josephson junctions are the active elements for RSFQ electronics, just as transistors are the active elements for semiconductor electronics. However, RSFQ is not a quantum computing technology in the traditional sense. Even so, RSFQ is very different from the traditional CMOS transistor technology used in every day computers due to its power efficiency and high speed it is being used.

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The growing market for fast floating-point coprocessors, digital signal processing chips, and graphics processors has created a demand for high speed, area efficient multipliers. Current architectures range from small, low-performance shift and add multipliers, to large, high-performance array and tree multipliers. Conventional linear array multipliers achieve high performance in a regular structure, but require large amounts of silicon. Tree structures achieve even higher performance than linear arrays but the tree interconnection is more complex and less regular, making them even larger than linear arrays. Ideally, one would want the speed benefits of a tree structure, the regularity of an array multiplier, and the small size of a shift and add multiplier. In electronics, rapid single flux quantum (RSFQ) is a digital electronics technology that relies on quantum effects in superconducting devices, namely Josephson junctions, to process digital signals. Josephson junctions are the active elements for RSFQ electronics, just as transistors are the active elements for semiconductor electronics. However, RSFQ is not a quantum computing technology in the traditional sense. Even so, RSFQ is very different from the traditional CMOS transistor technology used in every day computers due to its power efficiency and high speed it is being used.
Rapid Single Flux Quantum (RSFQ) Josephson-junction technology is capable of processing digital data at sub-terahertz frequencies while dissipating almost negligible power. At the present time one can routinely simulate, optimize, design, manufacture, and test an elementary RSFQ logic/memory cell consisting of dozens of Josephson junctions. Furthermore, a number of relatively complex (few hundred to few thousand Josephson junctions) digital circuits were designed and successfully tested. Moreover we know how to implement several RSFQ systems (including analog-to-digital and digital-to-analog converters, digital SQUIDs for supersensitive magnetometry, and digital autocorrelator for radioastronomy) which would far outperform their currently available and even prospective semiconductor counterparts. In order to implement more complex RSFQ systems, including high-performance digital signal processors and general purpose computers there are a number of technical problems to solve. The issues include making full use of on-chip sub-terahertz processing in conditions when inter-chip data/clock exchange speed is bound by bandwidth of the order of a few Gbps/pin. I present the current know-how of the field, and formulate the questions that need to be solved before the RSFQ technology becomes a major workhorse of high-performance computation.
Superconductor digital technology based on Rapid Single Flux Quantum logic (RSFQ) offers more than 50 times gain in speed and more than 100 reduction in power consumption over mainstream CMOS devices. However, the necessity of cooling down to 4 K and modest degree of integration density currently available mean that employing RSFQ is reasonable only for the tasks that are impossible or ineffective to implement in CMOS technology. One of the promising applications of the RSFQ technology is Digital Signal Processing (DSP) for telecommunications. Interference cancellation is a bottleneck for all existing systems in terms of the performance gain that is theoretically possible and technically realizable using conventional technology. The crucial factor is computational complexity required to handle multiple access interference. The general approach is to compute the interference using available data about propagation channels and then either remove it from received signal or use to predistort the transmitted signal. Computation of the interference matrix can easily fall into 100 Gops range, furthermore, the most e±cient algorithms are based on successive iterations. This requires not only high overall performance of the DSP but also high actual clock rate.This thesis reports a proposed architecture of an RSFQ Successive Interference Canceller and a design of an RSFQ Digital Signal Processor based on hybrid RSFQ-CMOS memory suitable for a general matrix on matrix multiplication algorithm. The processor consists of an RSFQ Multiply-Accumulate Unit, memory caches and a synchronization block, partitioned into multiple chips, and a large CMOS memory.The complexity of the RSFQ DSP is 10x10 multiplication, rounding to 14 bits, 18 bits accumulator length and 3.7 Kb memory cache. In order to implement the RSFQ DSP, we have developed approach to simulate and describe the RSFQ circuits using VHDL. The maximum simulated clock frequency is equal to 24 GHz for Hypres 4.5 kA/cm2 process and optimum communication bandwidth with CMOS memory is 2 Gbps.Components of the processor such as 4x4 two's complement and 5x5 parallel multipliers, 4x5, 20x5 and 4x15 parallel shift registers, a 5-bit serial adder have been designed and experimentally tested. The simplified version of the RSFQ DSP consisting of a 4x4 MAC with rounding to 5 bits and 17x6 memory caches has been designed for Hypres 4.5 kA/cm2 process and fabricated.
Key digital circuits for signal processing with tens of gigahertz speed and a few microwatts power dissipation have been recently demonstrated using a simple, 2 /spl mu/m linewidth process. These are the fastest digital circuits reported to date. These circuits use novel rapid single flux quantum (RSFQ) technology that takes advantage of the fundamental properties of superconductivity. In this technology, data and clock are picosecond-long quantized voltage pulses corresponding to the transfer of single magnetic flux quanta, /spl Phisub 0/=h/2e=2 mVps. These SFQ pulses are regenerated at each gate and are processed by circuits comprised of overdamped Josephson junctions interconnected via microstrip inductances. The inherent internal memory of all RSFQ gates (primarily flip-flops), combined with high switching speed, makes serial, bit-pipelined circuit design advantageous. This paper presents experiments in RSFQ digital circuits, including an N/spl times/8b serial multiplier, and on-chip test systems based on RSFQ shift registers and on SFQ samplers. They enable test and study of RSFQ circuits at full GHz speed while communicating with semiconductor electronics at low speed.>
The Rapid Single-Flux-Quantum logic (RSFQ) presents an efficient way to achieve ultra fast digital operations. This logic uses the macroscopic effects which can be found in nano-structured superconductor devices such as the Josephson AC and DC effects, and the magnetic flux quantization. As the typical time of the Josephson junction quantized phase leap 2π is in the order of picoseconds, the RSFQ circuits can operate with clock frequencies in the order of hundreds of GHz. This invited paper focuses on basic principles of superconducting RSFQ logic as well as on typical applications, such as the signal conversion or petaflops computing systems. In addition we point out the benefits of the semi-metallic NbN-TaxN-NbN Josephson junction technology, which has been developed at CEA-INAC in Grenoble.
Abstract: We have developed and experimentally evaluated at high-speed, a complete set of arithmetic circuits (multiply, add, and accumulate) for high performance digital signal processing (DSP). These circuits take advantage of the unique features of the Rapid Single-Flux Quantum (RSFQ) logic/memory family, including fusion of logic and memory functions at the gate level, pulse representation of clock and data, and the ability to maintain inter cell propagation delays using Josephson transmission lines (JTLs). The circuits developed have been successfully used in the implementation of a serial radix 2 butterfly, a decimation digital filter, and of an arithmetic unit for digital beam forming. The 8×8-bit RSFQ multiplier uses a two- level parallel carry- save reduction tree that significantly reduces the multiplier latency. The 80-GHz carry-save reduction is implemented with asynchronous data-driven wave pipelined [4:2] compressors built with toggle flip-flop cells.
Advancement of superconductor digital electronics, especially Rapid Single Flux Quantum (RSFQ) logic circuit is described. Ultra short pulse of a voltage generated across a Josephson junction and release from charging/discharging process for signal transmission in RSFQ circuits enable us to reduce power consumption and gate delay. The power-delay products (PDPs) of RSFQ integrated circuits (ICs) are 4 or 5 orders of magnitude smaller than those of semiconductor ICs. The fabrication process technology and the related designing technology have been advanced, and RSFQ ICs have been applied to software-defined radio receivers, superconductor detector array systems, and supercomputers. Recently, several kinds of energy-efficient single flux quantum circuit have been proposed to obtain further advantage to semiconductor devices. The PDPs of these circuits become at least 1 order smaller than those of conventional RSFQ circuits.