It is well-known that the presence of cycles in a factor graph degrades the performance of message-passing algorithms due to the violation of the assumption of statistical independence of messages.While finding and counting all cycles in a graph is a very hard problem, efficient algorithms have been proposed recently to find all short cycles up to some maximum length.For the message-passing decoding of Low-Density Parity-Check (LDPC) codes, these short cycles are the main cause for the existing performance gap to optimal Maximum Likelihood (ML) decoding.In this paper, we exploit this observation in the proposed novel method of realizing rate-compatible (RC) LDPC codes with short block lengths by inserting known dummy bits into the information bit sequence before encoding.This technique can be seen as a special case of traditional code shortening and allows to achieve lower code rates using one fixed rate mother code.The novelty of the proposed method lies in the selection of the specific dummy bit positions in a way that "breaks" a significant number of short cycles in the mother code's graph which, thus, no longer degrade the decoding performance.
It is well-known that the presence of cycles in a factor graph degrades the performance of message-passing algorithms due to the violation of the assumption of statistical independence of messages.While finding and counting all cycles in a graph is a very hard problem, efficient algorithms have been proposed recently to find all short cycles up to some maximum length.For the message-passing decoding of Low-Density Parity-Check (LDPC) codes, these short cycles are the main cause for the existing performance gap to optimal Maximum Likelihood (ML) decoding.In this paper, we exploit this observation in the proposed novel method of realizing rate-compatible (RC) LDPC codes with short block lengths by inserting known dummy bits into the information bit sequence before encoding.This technique can be seen as a special case of traditional code shortening and allows to achieve lower code rates using one fixed rate mother code.The novelty of the proposed method lies in the selection of the specific dummy bit positions in a way that "breaks" a significant number of short cycles in the mother code's graph which, thus, no longer degrade the decoding performance.
Error control coding is an essential part of modern communications systems. LDPC codes have been demonstrated to offer performance near the fundamental limits of channels corrupted by random noise. Optimal maximum likelihood decoding of LDPC codes is too complex to be practically useful even at short block lengths and so a graph-based message passing decoder known as the belief propagation algorithm is used instead. In fact, on graphs without closed paths known as cycles the iterative message passing decoding is known to be optimal and may converge in a single iteration, although identifying the message update schedule which allows single-iteration convergence is not trivial. At finite block lengths graphs without cycles have poor minimum distance properties and perform poorly even under optimal decoding. LDPC codes with large block length have been demonstrated to offer performance close to that predicted for codes of infinite length, as the cycles present in the graph are quite long. In this thesis, LDPC codes of shorter length are considered as they offer advantages in terms of latency and complexity, at the cost of performance degradation from the increased number of short cycles in the graph. For these shorter LDPC codes, the problems considered are: \n \nFirst, improved construction of structured and unstructured LDPC code graphs of short length with a view to reducing the harmful effects of the cycles on error rate performance, based on knowledge of the decoding process. Structured code graphs are particularly interesting as they allow benefits in encoding and decoding complexity and speed. Secondly, the design and construction of LDPC codes for the block fading channel, a particularly challenging scenario from the point of view of error control code design. Both established and novel classes of codes for the channel are considered. Finally the decoding of LDPC codes by the belief propagation algorithm is considered, in particular the scheduling of messages passed in the iterative decoder. A knowledge-aided approach is developed based on message reliabilities and residuals to allow fast convergence and significant improvements in error rate performance.
It is well known that extremely long low-density parity-check (LDPC) codes perform exceptionally well for error correction applications, short-length codes are preferable in practical applications. However, short-length LDPC codes suffer from performance degradation owing to graph-based impairments such as short cycles, trapping sets and stopping sets and so on in the bipartite graph of the LDPC matrix. In particular, performance degradation at moderate to high Eb/N0 is caused by the oscillations in bit node a posteriori probabilities induced by short cycles and trapping sets in bipartite graphs. In this study, a computationally efficient algorithm is proposed to improve the performance of short-length LDPC codes at moderate to high Eb/N0. This algorithm makes use of the information generated by the belief propagation (BP) algorithm in previous iterations before a decoding failure occurs. Using this information, a reliability-based estimation is performed on each bit node to supplement the BP algorithm. The proposed algorithm gives an appreciable coding gain as compared with BP decoding for LDPC codes of a code rate equal to or less than 1/2 rate coding. The coding gains are modest to significant in the case of optimised (for bipartite graph conditioning) regular LDPC codes, whereas the coding gains are huge in the case of unoptimised codes. Hence, this algorithm is useful for relaxing some stringent constraints on the graphical structure of the LDPC code and for developing hardware-friendly designs.
In this digital era, modern communication systems play an essential part in nearly every aspect of life, with examples ranging from mobile networks and satellite communications to Internet and data transfer. Unfortunately, all communication systems in a practical setting are noisy, which indicates that we can either improve the physical characteristics of the channel or find a possible systematical solution, i.e. error control coding. The history of error control coding dates back to 1948 when Claude Shannon published his celebrated work “A Mathematical Theory of Communication”, which built a framework for channel coding, source coding and information theory. For the first time, we saw evidence for the existence of channel codes, which enable reliable communication as long as the information rate of the code does not surpass the so-called channel capacity. Nevertheless, in the following 60 years none of the codes have been proven closely to approach the theoretical bound until the arrival of turbo codes and the renaissance of LDPC codes. As a strong contender of turbo codes, the advantages of LDPC codes include parallel implementation of decoding algorithms and, more crucially, graphical construction of codes. However, there are also some drawbacks to LDPC codes, e.g. significant performance degradation due to the presence of short cycles or very high decoding latency. In this thesis, we will focus on the practical realisation of finite-length LDPC codes and devise algorithms to tackle those issues.
Firstly, rate-compatible (RC) LDPC codes with short/moderate block lengths are investigated on the basis of optimising the graphical structure of the tanner graph (TG), in order to achieve a variety of code rates (0.1 < R < 0.9) by only using a single encoder-decoder pair. As is widely recognised in the literature, the presence of short cycles considerably reduces the overall performance of LDPC codes which significantly limits their application in communication systems. To reduce the impact of short cycles effectively for different code rates, algorithms for counting short cycles and a graph-related metric called Extrinsic Message Degree (EMD) are applied with the development of the proposed puncturing and extension techniques. A complete set of simulations are carried out to demonstrate that the proposed RC designs can largely minimise the performance loss caused by puncturing or extension.
Secondly, at the decoding end, we study novel decoding strategies which compensate for the negative effect of short cycles by reweighting part of the extrinsic messages exchanged between the nodes of a TG. The proposed reweighted belief propagation (BP) algorithms aim to implement efficient decoding, i.e. accurate signal reconstruction and low decoding latency, for LDPC codes via various design methods. A variable factor appearance probability belief propagation (VFAP-BP) algorithm is proposed along with an improved version called a locally-optimized reweighted (LOW)-BP algorithm, both of which can be employed to enhance decoding performance significantly for regular and irregular LDPC codes. More importantly, the optimisation of reweighting parameters only takes place in an offline stage so that no additional computational complexity is required during the real-time decoding process.
Lastly, two iterative detection and decoding (IDD) receivers are presented for multiple-input multiple-output (MIMO) systems operating in a spatial multiplexing configuration. QR decomposition (QRD)-type IDD receivers utilise the proposed multiple-feedback (MF)-QRD or variable-M (VM)-QRD detection algorithm with a standard BP decoding algorithm, while knowledge-aided (KA)-type receivers are equipped with a simple soft parallel interference cancellation (PIC) detector and the proposed reweighted BP decoders. In the uncoded scenario, the proposed MF-QRD and VM-QRD algorithms are shown to approach optimal performance, yet require a reduced computational complexity. In the LDPC-coded scenario, simulation results have illustrated that the proposed QRD-type IDD receivers can offer near-optimal performance after a small number of detection/decoding iterations and the proposed KA-type IDD receivers significantly outperform receivers using alternative decoding algorithms, while requiring similar decoding complexity.
Information technology, at present has thrived to great aspects and every day more beneficiary of this blessing is being connected to the modern invention and technology. With the swift growth of communication networks, there has been a high demand for efficient and reliable digital transmission and data storage system. LDPC is one of the channel codes for error correcting that have been developed for competent systems that require higher reliability. For low-end devices requiring a limited battery or computational power, low complexity decoders are useful. For LDPC codes, the presence of short cycle in the parity-check matrix lower the decoding threshold making it less efficient. In this research, a method has been developed from an existing algorithm that finds out the exact position of potential bits forming cycle-4 in the parity check matrix that might create decoding failure after transmission in binary erasure channel. Once the short cycles are detected, it can be removed by puncturing method to obtain capacity achieving codes. The code obtained by the method has a threshold 0.42 and rate 0.5, which is asymptotically close to the mother code. Simulations show that for less number of iterations and in the presence of same channel erasure the decoder block error probability close to 10-6 is achievable. As no other additional decoding algorithm is employed, the proposed scheme does not add additional computational complexity to the decoder. Furthermore, as an extension to the method a scheme has been proposed to generate rate-compatible LDPC codes using 0.5 rate regular code with puncturing method varying puncturing fractions. By the proposed method of generating different rate code, same amount of information can be sent with less parity.
In this paper, we propose a rate-compatible puncturing scheme for finite-length low-density parity-check (LDPC) codes over the additive white Gaussian noise (AWGN) channel. The proposed method is applicable to any LDPC mother code, both regular and irregular, and constructs punctured codes which perform well in both the waterfall and the error floor regions for a wide range of code rates. The scheme selects code bits to be punctured one at a time and based on a sequence of criteria. An important selection criterion is the number of short cycles with low approximate cycle extrinsic message degree (ACE) in which a candidate bit node participates. Simulation results demonstrate that the ACE measure, which is most often the determining criterion in the final selection of the puncturing candidates, plays an important role in improving the performance of the codes in both the waterfall and the error-floor regions. These results also demonstrate that the proposed scheme is superior to the existing puncturing methods, particularly when a wide range of code rates is desirable.
This paper presents a cycle-based rate-compatible puncturing technique for non-binary (NB) low-density parity-check (LDPC) codes. The proposed puncturing technique is based on the connectivity of the short non-binary (NB) cycles present in the Tanner graph. The connectivity of a cycle is measured by the extrinsic message degree (EMD). The short cycles with low values of EMD degrade the performance of iterative decoders significantly. The proposed technique selects the variable nodes for puncturing by reckoning their involvements in the short NB cycles with a low EMD. Simulations in different contexts are performed to check the efficiency of the proposed technique.