Information technology, at present has thrived to great aspects and every day more beneficiary of this blessing is being connected to the modern invention and technology. With the swift growth of communication networks, there has been a high demand for efficient and reliable digital transmission and data storage system. LDPC is one of the channel codes for error correcting that have been developed for competent systems that require higher reliability. For low-end devices requiring a limited battery or computational power, low complexity decoders are useful. For LDPC codes, the presence of short cycle in the parity-check matrix lower the decoding threshold making it less efficient. In this research, a method has been developed from an existing algorithm that finds out the exact position of potential bits forming cycle-4 in the parity check matrix that might create decoding failure after transmission in binary erasure channel. Once the short cycles are detected, it can be removed by puncturing method to obtain capacity achieving codes. The code obtained by the method has a threshold 0.42 and rate 0.5, which is asymptotically close to the mother code. Simulations show that for less number of iterations and in the presence of same channel erasure the decoder block error probability close to 10-6 is achievable. As no other additional decoding algorithm is employed, the proposed scheme does not add additional computational complexity to the decoder. Furthermore, as an extension to the method a scheme has been proposed to generate rate-compatible LDPC codes using 0.5 rate regular code with puncturing method varying puncturing fractions. By the proposed method of generating different rate code, same amount of information can be sent with less parity.
Information technology, at present has thrived to great aspects and every day more beneficiary of this blessing is being connected to the modern invention and technology. With the swift growth of communication networks, there has been a high demand for efficient and reliable digital transmission and data storage system. LDPC is one of the channel codes for error correcting that have been developed for competent systems that require higher reliability. For low-end devices requiring a limited battery or computational power, low complexity decoders are useful. For LDPC codes, the presence of short cycle in the parity-check matrix lower the decoding threshold making it less efficient. In this research, a method has been developed from an existing algorithm that finds out the exact position of potential bits forming cycle-4 in the parity check matrix that might create decoding failure after transmission in binary erasure channel. Once the short cycles are detected, it can be removed by puncturing method to obtain capacity achieving codes. The code obtained by the method has a threshold 0.42 and rate 0.5, which is asymptotically close to the mother code. Simulations show that for less number of iterations and in the presence of same channel erasure the decoder block error probability close to 10-6 is achievable. As no other additional decoding algorithm is employed, the proposed scheme does not add additional computational complexity to the decoder. Furthermore, as an extension to the method a scheme has been proposed to generate rate-compatible LDPC codes using 0.5 rate regular code with puncturing method varying puncturing fractions. By the proposed method of generating different rate code, same amount of information can be sent with less parity.
In this digital era, modern communication systems play an essential part in nearly every aspect of life, with examples ranging from mobile networks and satellite communications to Internet and data transfer. Unfortunately, all communication systems in a practical setting are noisy, which indicates that we can either improve the physical characteristics of the channel or find a possible systematical solution, i.e. error control coding. The history of error control coding dates back to 1948 when Claude Shannon published his celebrated work “A Mathematical Theory of Communication”, which built a framework for channel coding, source coding and information theory. For the first time, we saw evidence for the existence of channel codes, which enable reliable communication as long as the information rate of the code does not surpass the so-called channel capacity. Nevertheless, in the following 60 years none of the codes have been proven closely to approach the theoretical bound until the arrival of turbo codes and the renaissance of LDPC codes. As a strong contender of turbo codes, the advantages of LDPC codes include parallel implementation of decoding algorithms and, more crucially, graphical construction of codes. However, there are also some drawbacks to LDPC codes, e.g. significant performance degradation due to the presence of short cycles or very high decoding latency. In this thesis, we will focus on the practical realisation of finite-length LDPC codes and devise algorithms to tackle those issues.
Firstly, rate-compatible (RC) LDPC codes with short/moderate block lengths are investigated on the basis of optimising the graphical structure of the tanner graph (TG), in order to achieve a variety of code rates (0.1 < R < 0.9) by only using a single encoder-decoder pair. As is widely recognised in the literature, the presence of short cycles considerably reduces the overall performance of LDPC codes which significantly limits their application in communication systems. To reduce the impact of short cycles effectively for different code rates, algorithms for counting short cycles and a graph-related metric called Extrinsic Message Degree (EMD) are applied with the development of the proposed puncturing and extension techniques. A complete set of simulations are carried out to demonstrate that the proposed RC designs can largely minimise the performance loss caused by puncturing or extension.
Secondly, at the decoding end, we study novel decoding strategies which compensate for the negative effect of short cycles by reweighting part of the extrinsic messages exchanged between the nodes of a TG. The proposed reweighted belief propagation (BP) algorithms aim to implement efficient decoding, i.e. accurate signal reconstruction and low decoding latency, for LDPC codes via various design methods. A variable factor appearance probability belief propagation (VFAP-BP) algorithm is proposed along with an improved version called a locally-optimized reweighted (LOW)-BP algorithm, both of which can be employed to enhance decoding performance significantly for regular and irregular LDPC codes. More importantly, the optimisation of reweighting parameters only takes place in an offline stage so that no additional computational complexity is required during the real-time decoding process.
Lastly, two iterative detection and decoding (IDD) receivers are presented for multiple-input multiple-output (MIMO) systems operating in a spatial multiplexing configuration. QR decomposition (QRD)-type IDD receivers utilise the proposed multiple-feedback (MF)-QRD or variable-M (VM)-QRD detection algorithm with a standard BP decoding algorithm, while knowledge-aided (KA)-type receivers are equipped with a simple soft parallel interference cancellation (PIC) detector and the proposed reweighted BP decoders. In the uncoded scenario, the proposed MF-QRD and VM-QRD algorithms are shown to approach optimal performance, yet require a reduced computational complexity. In the LDPC-coded scenario, simulation results have illustrated that the proposed QRD-type IDD receivers can offer near-optimal performance after a small number of detection/decoding iterations and the proposed KA-type IDD receivers significantly outperform receivers using alternative decoding algorithms, while requiring similar decoding complexity.
This paper first introduces an improved decoding algorithm for low-density parity-check (LDPC) codes over binary-input-output-symmetric memoryless channels. Then some fundamental properties of punctured LDPC codes are presented. It is proved that for any ensemble of LDPC codes, there exists a puncturing threshold. It is then proved that for any rates R1and R2satisfying 0121to R2resulting in asymptotically good codes for all rates R1lesRlesR2. Specifically, this implies that rates arbitrarily close to one are achievable via puncturing. Bounds on the performance of punctured LDPC codes are also presented. It is also shown that punctured LDPC codes are as good as ordinary LDPC codes. For BEC and arbitrary positive numbers R121lesRlesR2is shown. Based on the above observations, a method is proposed to design good punctured LDPC codes over a broad range of rates. Finally, it is shown that the results of this paper may be used for the proof of the existence of the capacity-achieving LDPC codes over binary-input-output-symmetric memoryless channels
With the rapid expansion of communication networks, there has been an increasing demand for efficient and reliable digital data transmission and storage systems. Many efficient codes have been developed. The LDPC code is one of them. In this thesis, the sum-product algorithm is used in the decoding of LDPC codes. Some schemes for encoding LDPC codes have been studied. In particular, two methods of producing regular H matrices have been attempted that include short cycles of length four with code rates of 0.5, and we present three schemes of finding regular H matrices which do not include short cycles of length four with code rate being 0.5. The effect of short cycles in the bipartite graph of regular LDPC codes has been considered. The simulation results show that the BER performances of regular H matrices that do not include short cycles of length four based on BPSK or 8PSK on AWGN channel is better than those of regular H matrices that include short cycles of length four. In conclusion, in order to obtain good performance with LDPC code, one should design H matrix related to bipartite graph without short cycles.
The Low Density Parity Check (LDPC) are direct codes, which are true block and Shannon Limit codes.These codes are attained least error floors of data bits for data transfer applications used in communication systems.However, the proposed LDPC codes are more beneficial than Turbo codes because of reduction in the decoding complexity and detection of the errors in less cycle time.This results the reduction of decoding time, low decoding latency, complexity and as well as least error floorings in communication, when the transmitted data contains multiple error bits.This paper is proposed to represent the majority logic decoding/detecting of LDPC codes.This paper proposes the Generation of Originator and Parity estimated matrices for the Binary LDPC Codes.Here, the proposed techniques are hard decision decrypting and soft decision decrypting schemes.These schemes uses majority logic decoding based on the data transmission and reception in communication channel.This paper also elaborates the effective calculation of Euclidean distance and algorithm for constructing the LDPC codes.
This paper investigates the construction of random-structure LDPC (low-density parity-check) codes using Progressive Edge-Growth (PEG) algorithm and two proposed algorithms for removing short cycles (CB1 and CB2 algorithm; CB stands for Cycle Break). Progressive Edge-Growth is an algorithm for computer-based design of random-structure LDPC codes, the role of which is to generate a Tanner graph (a bipartite graph, which represents a parity-check matrix of an error-correcting channel code) with as few short cycles as possible. Short cycles, especially the shortest ones with a length of 4 edges, in Tanner graphs of LDPC codes can degrade the performance of their decoding algorithm, because after certain number of decoding iterations, the information sent through its edges is no longer independent. The main contribution of this paper is the unique approach to the process of removing short cycles in the form of CB2 algorithm, which erases edges from the code's parity-check matrix without decreasing the minimum Hamming distance of the code. The two cycle-removing algorithms can be used to improve the error-correcting performance of PEG-generated (or any other) LDPC codes and achieved results are provided. All these algorithms were used to create a PEG LDPC code which rivals the best-known PEG-generated LDPC code with similar parameters provided by one of the founders of LDPC codes. The methods for generating the mentioned error-correcting codes are described along with simulations which compare the error-correcting performance of the original codes generated by the PEG algorithm, the PEG codes processed by either CB1 or CB2 algorithm and also external PEG code published by one of the founders of LDPC codes
It is well known that extremely long low-density parity-check (LDPC) codes perform exceptionally well for error correction applications, short-length codes are preferable in practical applications. However, short-length LDPC codes suffer from performance degradation owing to graph-based impairments such as short cycles, trapping sets and stopping sets and so on in the bipartite graph of the LDPC matrix. In particular, performance degradation at moderate to high Eb/N0 is caused by the oscillations in bit node a posteriori probabilities induced by short cycles and trapping sets in bipartite graphs. In this study, a computationally efficient algorithm is proposed to improve the performance of short-length LDPC codes at moderate to high Eb/N0. This algorithm makes use of the information generated by the belief propagation (BP) algorithm in previous iterations before a decoding failure occurs. Using this information, a reliability-based estimation is performed on each bit node to supplement the BP algorithm. The proposed algorithm gives an appreciable coding gain as compared with BP decoding for LDPC codes of a code rate equal to or less than 1/2 rate coding. The coding gains are modest to significant in the case of optimised (for bipartite graph conditioning) regular LDPC codes, whereas the coding gains are huge in the case of unoptimised codes. Hence, this algorithm is useful for relaxing some stringent constraints on the graphical structure of the LDPC code and for developing hardware-friendly designs.