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International Conference on Signal Processing and Communications (SPCOM)

A cycle-based rate-compatible puncturing technique for non-binary LDPC codes

Kuntal Deka, A. Rajesh, Prabin Kumar Bora

Published Jun 1, 2016• 1 citation
Publisher

Abstract

This paper presents a cycle-based rate-compatible puncturing technique for non-binary (NB) low-density parity-check (LDPC) codes. The proposed puncturing technique is based on the connectivity of the short non-binary (NB) cycles present in the Tanner graph. The connectivity of a cycle is measured by the extrinsic message degree (EMD). The short cycles with low values of EMD degrade the performance of iterative decoders significantly. The proposed technique selects the variable nodes for puncturing by reckoning their involvements in the short NB cycles with a low EMD. Simulations in different contexts are performed to check the efficiency of the proposed technique.

DOI
10.1109/spcom.2016.7746650

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This paper presents a cycle-based rate-compatible puncturing technique for non-binary (NB) low-density parity-check (LDPC) codes. The proposed puncturing technique is based on the connectivity of the short non-binary (NB) cycles present in the Tanner graph. The connectivity of a cycle is measured by the extrinsic message degree (EMD). The short cycles with low values of EMD degrade the performance of iterative decoders significantly. The proposed technique selects the variable nodes for puncturing by reckoning their involvements in the short NB cycles with a low EMD. Simulations in different contexts are performed to check the efficiency of the proposed technique.
This paper presents an improvement of a puncturing technique for rate-compatible low density parity check (LDPC) codes originally proposed by Asvadi and Banihashemi. In the original technique, the puncturing bits are selected by progressively reducing the search space according to a certain sequence of criteria. The last criterion is based on the ACE (approximate cycle extrinsic message degree) values of the short cycles present in the Tanner graph of the code. In this paper, we propose to substitute the last criterion with one which is based on the absorbing sets of the code. Simulation results show that this scheme improves the performance compared to the original and some other scheme available in the literature.
In this paper, we investigate rate-compatible (RC) short/ moderate length irregular low-density parity-check (LDPC) codes and propose three different novel puncturing schemes to determine the preferred puncturing positions so as to achieve less performance degradation. The first one is based on a short cycle counting algorithm as well as grouping variable nodes which have the equal length of short cycles in the Tanner Graph; the second scheme can be seen as an improved version of the first one by means of introducing another metric called Extrinsic Message Degree (EMD); and the last scheme relies on a simulation-based exhaustive search in order to find the best puncturing pattern among several random puncturing patterns. The simulation results show that all three proposed schemes can achieve the rate flexibility and minimize the performance loss over the additive white Gaussian noise (AWGN) channel.
This paper propose a rate-compatible puncturing scheme for finite-length low-density parity-check(LDPC) codes over the additive white Gaussian noise(AWGN)channel.The method can applicable to both regular and irregular LDPC code.The scheme selects bits to be punctured base on a sequence of criteria.An important selection criterion is the number of short cycles with low approximate cycle extrinsic message degree(ACE)in which a candidate bit node participates.Simulation results demonstrate that the ACE plays an important role in the performance of the codes,these results also show that the scheme is superior to the existing puncturing methods in a wide range of code rates.
In this paper, we propose a rate-compatible puncturing scheme for finite-length low-density parity-check (LDPC) codes over the additive white Gaussian noise (AWGN) channel. The proposed method is applicable to any LDPC mother code, both regular and irregular, and constructs punctured codes which perform well in both the waterfall and the error floor regions for a wide range of code rates. The scheme selects code bits to be punctured one at a time and based on a sequence of criteria. An important selection criterion is the number of short cycles with low approximate cycle extrinsic message degree (ACE) in which a candidate bit node participates. Simulation results demonstrate that the ACE measure, which is most often the determining criterion in the final selection of the puncturing candidates, plays an important role in improving the performance of the codes in both the waterfall and the error-floor regions. These results also demonstrate that the proposed scheme is superior to the existing puncturing methods, particularly when a wide range of code rates is desirable.
A family of rate-compatible (RC) punctured low-density parity-check convolutional codes (LDPC-CCs) is derived from an LDPC-CC by periodically puncturing encoded bits (variable nodes) with respect to several criteria: (1) ensuring the recoverability of punctured variable nodes, (2) minimizing the number of completely punctured cycle trapping sets (CPCTSs), and (3) minimizing the number of punctured variable nodes involved in short cycles. As an example, a family of RC punctured LDPC-CCs with rates 4/9, 4/8, 4/7, 4/6, and 4/5 are obtained from the (21,3, 5) Tanner LDPC-CC.
It is well-known that the presence of cycles in a factor graph degrades the performance of message-passing algorithms due to the violation of the assumption of statistical independence of messages.While finding and counting all cycles in a graph is a very hard problem, efficient algorithms have been proposed recently to find all short cycles up to some maximum length.For the message-passing decoding of Low-Density Parity-Check (LDPC) codes, these short cycles are the main cause for the existing performance gap to optimal Maximum Likelihood (ML) decoding.In this paper, we exploit this observation in the proposed novel method of realizing rate-compatible (RC) LDPC codes with short block lengths by inserting known dummy bits into the information bit sequence before encoding.This technique can be seen as a special case of traditional code shortening and allows to achieve lower code rates using one fixed rate mother code.The novelty of the proposed method lies in the selection of the specific dummy bit positions in a way that "breaks" a significant number of short cycles in the mother code's graph which, thus, no longer degrade the decoding performance.