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Revista Facultad de Ingeniería Universidad de Antioquia

Hardware emulation of quantum circuits based on Toffoli gates

Jaime Velasco-Medina, Jorge E. Duarte-Sánchez

Published May 28, 2014• 0 citations
Publisher

Abstract

This work presents the design of a hardware architecture for the emulation of quantum circuits based on Toffoli gates allowing the emulation of more than 50 qubits. The state of the system is obtained processing each basis state by means of the functions determined by the quantum gates for each qubit; the time required to execute the emulation grows exponentially only with the number of qubits that are used to generate a superposition of states, but not with the total amount of qubits of the system as occurs when the conventional matrix representation is used. Additionally, an array of processing units was designed to decrease the execution time. The synthesis results allow concluding that 9.35 seconds are required to emulate the 8-bit modular exponentiation, which uses 48 qubits, 155,312 quantum gates and requires processing 131,072 basis states. Furthermore these results allow estimating that 256 processing units of 52 qubits can be implemented in the FPGA EP3C120F780I7.

DOI
10.17533/udea.redin.19660

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This work presents the design of a hardware architecture for the emulation of quantum circuits based on Toffoli gates allowing the emulation of more than 50 qubits. The state of the system is obtained processing each basis state by means of the functions determined by the quantum gates for each qubit; the time required to execute the emulation grows exponentially only with the number of qubits that are used to generate a superposition of states, but not with the total amount of qubits of the system as occurs when the conventional matrix representation is used. Additionally, an array of processing units was designed to decrease the execution time. The synthesis results allow concluding that 9.35 seconds are required to emulate the 8-bit modular exponentiation, which uses 48 qubits, 155,312 quantum gates and requires processing 131,072 basis states. Furthermore these results allow estimating that 256 processing units of 52 qubits can be implemented in the FPGA EP3C120F780I7.
This work presents the design of a hardware architecture for the emulation of quantum circuits based on Toffoli gates allowing the emulation of more than 50 qubits. The state of the system is obtained processing each basis state by means of the functions determined by the quantum gates for each qubit; the time required to execute the emulation grows exponentially only with the number of qubits that are used to generate a superposition of states, but not with the total amount of qubits of the system as occurs when the conventional matrix representation is used. Additionally, an array of processing units was designed to decrease the execution time. The synthesis results allow concluding that 9.35 seconds are required to emulate the 8-bit modular exponentiation, which uses 48 qubits, 155,312 quantum gates and requires processing 131,072 basis states. Furthermore these results allow estimating that 256 processing units of 52 qubits can be implemented in the FPGA EP3C120F780I7.
A 16-qubit quantum-computing emulator executing quantum algorithms at high speed is proposed. By limiting the command of the quantum computing emulator to the minimum function required with the quantum algorithm, probability amplitudes are expressed with one bit and the functions of many qubits are integrated on a field programmable gate array (FPGA). As a result of implementing the emulator in the FPGA, it is found that the emulator has a 250 times higher-speed as compared with a software simulation by a general-purpose processor.
Hardware emulation based on field programmable gate array (FPGA) platform is vital to harness the power of quantum parallelism. As resource requirement grows exponentially in classical modeling quantum system, an optimum hardware architecture is crucial to emulate practical quantum circuits. Quantum Fourier transform (QFT) finds application in several critical quantum algorithms. In this work, experiments are conducted based on QFT to identify suitable qubit representation and hardware design technique. Experimental results show that 24-bit fixed point representation and serial architecture achieve optimal computation accuracy and resource utilization in QFT circuit emulation.
Current approaches for emulation of quantum algorithms on classical parallel hardware like FPGA suffer with three main issues: exponential usage of logic elements, synthesis takes exponential time and difficulty of implementation. In this paper we propose a processor architecture capable of efficiently emulate quantum circuits, reducing the mishaps of previous similar proposals. We compare our results to previous works with respect to a common benchmark and validate the architecture using FPGA. Our approach has better scalability in logic cell usage, a better management of the need of re-synthesis and easier implementation.
Abstract This paper presents a field-programmable gate array (FPGA) implementation of a quantum circuit simulator capable of processing 30-qubit systems, representing over 1.07 billion quantum states stored in 8 GB of memory. Built on the Xilinx Alveo U55C platform with High Bandwidth Memory (HBM) technology, our system demonstrates deterministic performance through a 16-bank parallel memory distribution architecture integrated with the Qiskit quantum computing framework. We achieved complete verification across all qubit configurations from 1 to 30 qubits, with execution times ranging from 5 milliseconds to approximately 49 minutes. The simulator supports a comprehensive quantum gate library including single-qubit operations (Hadamard, Pauli gates, rotation gates) and multi-qubit gates (CNOT, controlled-Z, Toffoli. Our performance analysis reveals distinct operational regimes where FPGA excels for small-scale circuits (1-12 qubits) but faces scalability challenges beyond 15 qubits when compared to GPU architectures. This work establishes FPGA as a practical platform for quantum algorithm development and circuit verification, particularly valuable for applications requiring deterministic timing and energy-efficient computation. The architecture provides clear pathways for expansion to 31+ qubits through memory configuration enhancements.