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Emulación en hardware de circuitos cuánticos basados en compuertas Toffoli Hardware emulation of quantum circuits based on Toffoli gates

Jorge E. Duarte-Sánchez, Jaime Velasco-Medina

Published Jan 1, 2014• 0 citations
OpenAlex

Abstract

This work presents the design of a hardware architecture for the emulation of quantum circuits based on Toffoli gates allowing the emulation of more than 50 qubits. The state of the system is obtained processing each basis state by means of the functions determined by the quantum gates for each qubit; the time required to execute the emulation grows exponentially only with the

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Hardware emulation of quantum circuits based on Toffoli gates

Jaime Velasco-Medina, Jorge E. Duarte-Sánchez

This work presents the design of a hardware architecture for the emulation of quantum circuits based on Toffoli gates allowing the emulation of more than 50 qubits. The state of the system is obtained processing each basis state by means of the functions determined by the quantum gates for each qubit; the time required to execute the emulation grows exponentially only with the number of qubits that are used to generate a superposition of states, but not with the total amount of qubits of the system as occurs when the conventional matrix representation is used. Additionally, an array of processing units was designed to decrease the execution time. The synthesis results allow concluding that 9.35 seconds are required to emulate the 8-bit modular exponentiation, which uses 48 qubits, 155,312 quantum gates and requires processing 131,072 basis states. Furthermore these results allow estimating that 256 processing units of 52 qubits can be implemented in the FPGA EP3C120F780I7.

Revista Facultad de Ingeniería Universidad de Antioquia•May 28, 2014•0 citations

Número completo 31

Revista Prometeica

This work presents the design of a hardware architecture for the emulation of quantum circuits based on Toffoli gates allowing the emulation of more than 50 qubits. The state of the system is obtained processing each basis state by means of the functions determined by the quantum gates for each qubit; the time required to execute the emulation grows exponentially only with the number of qubits that are used to generate a superposition of states, but not with the total amount of qubits of the system as occurs when the conventional matrix representation is used. Additionally, an array of processing units was designed to decrease the execution time. The synthesis results allow concluding that 9.35 seconds are required to emulate the 8-bit modular exponentiation, which uses 48 qubits, 155,312 quantum gates and requires processing 131,072 basis states. Furthermore these results allow estimating that 256 processing units of 52 qubits can be implemented in the FPGA EP3C120F780I7.

Prometeica - Revista de Filosofía y Ciencias•Nov 29, 2024•0 citations

Emulación en hardware de circuitos cuánticos basados en compuertas Toffoli

Jorge E. Duarte-Sánchez, Jaime Velasco-Medina

Este trabajo presenta el diseño de una arquitectura hardware para emular circuitos cuánticos basados en compuertas tipo Toffoli con la cual se pueden emular circuitos de más de 50 qubits. El estado del sistema se obtiene procesando independientemente cada estado base mediante las funciones determinadas por las compuertas cuánticas para cada qubit; el tiempo requerido para la emulación crece exponencialmente en función del número de qubits que se usan solamente para generar una superposición de estados, y no en función de la cantidad total de qubits del sistema como ocurre cuando se usa la representación matricial convencional. Adicionalmente, se diseñó un arreglo de unidades de procesamiento para disminuir el tiempo de ejecución. Los resultados de síntesis permiten concluir que se requieren 9,35 segundos para emular la exponenciación modular de 8 bits, la cual utiliza 48 qubits, 155.312 compuertas cuánticas y requiere procesar 131.072 estados base. Estos resultados también permiten estimar que se pueden implementar 256 unidades de procesamiento de 52 qubits en el FPGA EP3C120F780I7.

•Jan 1, 2014•0 citations

FPGA-based quantum circuit emulation: A case study on Quantum Fourier transform

Y. H. Lee, Mohamed Khalil-Hani, Muhammad Nadzir Marsono

Hardware emulation based on field programmable gate array (FPGA) platform is vital to harness the power of quantum parallelism. As resource requirement grows exponentially in classical modeling quantum system, an optimum hardware architecture is crucial to emulate practical quantum circuits. Quantum Fourier transform (QFT) finds application in several critical quantum algorithms. In this work, experiments are conducted based on QFT to identify suitable qubit representation and hardware design technique. Experimental results show that 24-bit fixed point representation and serial architecture achieve optimal computation accuracy and resource utilization in QFT circuit emulation.

International Symposium on Integrated Circuits•Dec 1, 2014•6 citations

Extending the Design Space of Dynamic Quantum Circuits for Toffoli based Network

Abhoy Kole, Arighna Deb, Kamalika Datta +1 more

Recent advances in fault tolerant quantum systems allow to perform non-unitary operations like mid-circuit measurement, active reset and classically controlled gate operations in addition to the existing unitary gate operations. Real quantum devices that support these non-unitary operations enable us to execute a new class of quantum circuits, known as Dynamic Quantum Circuits (DQC). This helps to enhance the scalability, thereby allowing execution of quantum circuits comprising of many qubits by using at least two qubits. Recently DQC realizations of multi-qubit Quantum Phase Estimation (QPE) and Bernstein-Vazirani (BV) algorithms have been demonstrated in two separate experiments. However the dynamic transformation of complex quantum circuits consisting of Toffoli gate operations have not been explored yet. This motivates us to: (a) explore the dynamic realization of Toffoli gates by extending the design space of DQC for Toffoli networks, and (b) propose a general dynamic transformation algorithm for the first time to the best of our knowledge. More precisely, we introduce two dynamic transformation schemes (dynamic-1 and dynamic-2) for Toffoli gates, that differ with respect to the required number of classically controlled gate operations. For evaluation, we consider the Deutsch-Jozsa (DJ) algorithm composed of one or more Toffoli gates. Experimental results demonstrate that dynamic DJ circuits based on dynamic-2 Toffoli realization scheme provides better computational accuracy over the dynamic-1 scheme. Further, the proposed dynamic transformation scheme is generic and can also be applied to non-Toffoli quantum circuits, e.g. BV algorithm.

Design, Automation, and Test in Europe•Apr 1, 2023•7 citations

An FPGA-based Emulation Process for Dynamic Quantum Circuits

Yicheng Song, Željko Žilić

The current quantum computation on physical devices has predominantly been constrained to basic, time-ordered sequences of unitary quantum operations culminating in a final projective measurement. As quantum computing hardware evolves in scale and functionality, it becomes crucial to facilitate the construction of quantum circuits beyond their traditional confines. Recent progress in quantum hardware has brought about mid-circuit measurements and resets, allowing for the recycling of measured qubits and notably decreasing the qubit demands for running quantum algorithms. We propose an FPGA-based dynamic quantum circuit emulation process to provide an emulation platform for designing and verifying dynamic quantum circuits.

International Symposium on Quality Electronic Design (ISQED)•Apr 23, 2025•3 citations
This work presents the design of a hardware architecture for the emulation of quantum circuits based on Toffoli gates allowing the emulation of more than 50 qubits. The state of the system is obtained processing each basis state by means of the functions determined by the quantum gates for each qubit; the time required to execute the emulation grows exponentially only with the
This work presents the design of a hardware architecture for the emulation of quantum circuits based on Toffoli gates allowing the emulation of more than 50 qubits. The state of the system is obtained processing each basis state by means of the functions determined by the quantum gates for each qubit; the time required to execute the emulation grows exponentially only with the number of qubits that are used to generate a superposition of states, but not with the total amount of qubits of the system as occurs when the conventional matrix representation is used. Additionally, an array of processing units was designed to decrease the execution time. The synthesis results allow concluding that 9.35 seconds are required to emulate the 8-bit modular exponentiation, which uses 48 qubits, 155,312 quantum gates and requires processing 131,072 basis states. Furthermore these results allow estimating that 256 processing units of 52 qubits can be implemented in the FPGA EP3C120F780I7.
This work presents the design of a hardware architecture for the emulation of quantum circuits based on Toffoli gates allowing the emulation of more than 50 qubits. The state of the system is obtained processing each basis state by means of the functions determined by the quantum gates for each qubit; the time required to execute the emulation grows exponentially only with the number of qubits that are used to generate a superposition of states, but not with the total amount of qubits of the system as occurs when the conventional matrix representation is used. Additionally, an array of processing units was designed to decrease the execution time. The synthesis results allow concluding that 9.35 seconds are required to emulate the 8-bit modular exponentiation, which uses 48 qubits, 155,312 quantum gates and requires processing 131,072 basis states. Furthermore these results allow estimating that 256 processing units of 52 qubits can be implemented in the FPGA EP3C120F780I7.
Este trabajo presenta el diseño de una arquitectura hardware para emular circuitos cuánticos basados en compuertas tipo Toffoli con la cual se pueden emular circuitos de más de 50 qubits. El estado del sistema se obtiene procesando independientemente cada estado base mediante las funciones determinadas por las compuertas cuánticas para cada qubit; el tiempo requerido para la emulación crece exponencialmente en función del número de qubits que se usan solamente para generar una superposición de estados, y no en función de la cantidad total de qubits del sistema como ocurre cuando se usa la representación matricial convencional. Adicionalmente, se diseñó un arreglo de unidades de procesamiento para disminuir el tiempo de ejecución. Los resultados de síntesis permiten concluir que se requieren 9,35 segundos para emular la exponenciación modular de 8 bits, la cual utiliza 48 qubits, 155.312 compuertas cuánticas y requiere procesar 131.072 estados base. Estos resultados también permiten estimar que se pueden implementar 256 unidades de procesamiento de 52 qubits en el FPGA EP3C120F780I7.
Hardware emulation based on field programmable gate array (FPGA) platform is vital to harness the power of quantum parallelism. As resource requirement grows exponentially in classical modeling quantum system, an optimum hardware architecture is crucial to emulate practical quantum circuits. Quantum Fourier transform (QFT) finds application in several critical quantum algorithms. In this work, experiments are conducted based on QFT to identify suitable qubit representation and hardware design technique. Experimental results show that 24-bit fixed point representation and serial architecture achieve optimal computation accuracy and resource utilization in QFT circuit emulation.
Recent advances in fault tolerant quantum systems allow to perform non-unitary operations like mid-circuit measurement, active reset and classically controlled gate operations in addition to the existing unitary gate operations. Real quantum devices that support these non-unitary operations enable us to execute a new class of quantum circuits, known as Dynamic Quantum Circuits (DQC). This helps to enhance the scalability, thereby allowing execution of quantum circuits comprising of many qubits by using at least two qubits. Recently DQC realizations of multi-qubit Quantum Phase Estimation (QPE) and Bernstein-Vazirani (BV) algorithms have been demonstrated in two separate experiments. However the dynamic transformation of complex quantum circuits consisting of Toffoli gate operations have not been explored yet. This motivates us to: (a) explore the dynamic realization of Toffoli gates by extending the design space of DQC for Toffoli networks, and (b) propose a general dynamic transformation algorithm for the first time to the best of our knowledge. More precisely, we introduce two dynamic transformation schemes (dynamic-1 and dynamic-2) for Toffoli gates, that differ with respect to the required number of classically controlled gate operations. For evaluation, we consider the Deutsch-Jozsa (DJ) algorithm composed of one or more Toffoli gates. Experimental results demonstrate that dynamic DJ circuits based on dynamic-2 Toffoli realization scheme provides better computational accuracy over the dynamic-1 scheme. Further, the proposed dynamic transformation scheme is generic and can also be applied to non-Toffoli quantum circuits, e.g. BV algorithm.
The current quantum computation on physical devices has predominantly been constrained to basic, time-ordered sequences of unitary quantum operations culminating in a final projective measurement. As quantum computing hardware evolves in scale and functionality, it becomes crucial to facilitate the construction of quantum circuits beyond their traditional confines. Recent progress in quantum hardware has brought about mid-circuit measurements and resets, allowing for the recycling of measured qubits and notably decreasing the qubit demands for running quantum algorithms. We propose an FPGA-based dynamic quantum circuit emulation process to provide an emulation platform for designing and verifying dynamic quantum circuits.