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IEEE International Symposium on Circuits and Systems proceedings

A scalable 3-phase polar decoder

Bertrand Le Gal, Camille Leroux, Christophe Jégo

Published May 1, 2016• 8 citations
Publisher

Abstract

In this paper, we propose a 3-phase polar codes Successive Cancellation (SC) decoder. Benefiting from the local properties of the decoding tree, 3 zones are defined and associated to 3 distinct sub-decoders. This approach reduces the memory footprint while guaranteeing a better scalability in comparison with state of the art SC decoders. Several 3-phase SC decoders are implemented on an FPGA circuit and compare favorably to state-of-the-art implementations in terms of distributed hardware resources (LUT, D-FF) and throughput. Moreover, the memory of the decoder is reduced by 37% for a N = 221polar codes.

DOI
10.1109/iscas.2016.7527259

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In this paper, we propose a 3-phase polar codes Successive Cancellation (SC) decoder. Benefiting from the local properties of the decoding tree, 3 zones are defined and associated to 3 distinct sub-decoders. This approach reduces the memory footprint while guaranteeing a better scalability in comparison with state of the art SC decoders. Several 3-phase SC decoders are implemented on an FPGA circuit and compare favorably to state-of-the-art implementations in terms of distributed hardware resources (LUT, D-FF) and throughput. Moreover, the memory of the decoder is reduced by 37% for a N = 221polar codes.
Polar codes are a family of error correcting codes that achieves the symmetric capacity of memoryless channels when the code length N tends to infinity. However, moderate code lengths are required in most of wireless digital applications to limit the decoding latency. In some other applications, such as optical communications or quantum key distribution, the latency introduced by very long codes is not an issue. The main challenge is to design codes with the best error correction capability, a tractable complexity and a high throughput. In such a context, SC decoding is an interesting solution because its performance improves with N while the computational complexity scales almost linearly. In this paper, we propose to improve the scalability of SC decoders thanks to four architectural optimizations. The resulting SC decoder is implemented on an FPGA device and favorably compares with state-of-the-art scalable SC decoders. Moreover, a 222polar code SC decoder is implemented on a Stratix-5 FPGA. This code length is twice larger than the ones achieved in previous works. To the best of our knowledge, this is the first architecture for which a N = 4 million bits polar code can be actually decoded on a reconfigurable circuit.
This paper proposes an effective field-programmable gate array (FPGA) implementation of a successive-cancellation (SC) decoder for polar codes that have recently attracted attention as error-correcting codes adopted for 5G wireless systems. We focus on effective ways of partitioning the SC decoding procedure into combinational and sequential logic parts. It can be shown that the SC decoder of length N(= N1N2) can be divided into two parts: N1SC decoders of length N2and a single SC decoder of length N1. While the N1decoders in the first part can perform in parallel, the decoding procedure in the second part is performed sequentially, which causes a bottleneck due to a long latency. We present an SC decoder architecture in which the first part is implemented using sequential logic circuits, and the second part is implemented using only combinational logic circuits. The overall latency and clock frequency of the decoder are balanced by the divisor N1of N, and we show that an appropriate choice of N1yields an efficient implementation with a high throughput. We demonstrate an FPGA implementation of the decoder architecture for a 1024-bit-length polar code and show that our FPGA decoder can achieve three times higher throughput than the conventional sequential semi-parallel decoder without significantly increasing the hardware resources.
Polar codes are one of the recently developed error correcting codes, and they are popular due to their capacity achieving nature. The architecture of the successive cancellation (SC) decoder algorithm is composed of a recursive processing element (PE). The PE comprises various blocks that include signed adder, subtractor, comparator, multiplexers, and few logic gates. Therefore, the latency of the PE is a primary concern. Hence, a high-speed architecture for implementing the SC decoding algorithm for polar codes is proposed. In the proposed work, a novel restructuring of the 2bit-SC (2b-SC) precomputation decoder architecture is carried out to reduce the latency by 20% while reducing the hardware complexity. Compared to the 2b-SC precomputation decoder, the proposed architecture also has 19% increased throughput for (1024, 512) polar codes with 45% reduction in the gate count.
This letter presents an efficient pruning method for the successive-cancellation (SC) decoding of polar codes. In the proposed method, unnecessary sub-trees are pruned if the syndrome check of a constituent code is satisfied. Without sacrificing the error-rate performance, the recursive operation associated with such a constituent code is replaced with simple computations. Compared with the traditional SC decoding, the proposed pruning decreases the decoding latency by 85% on the average for the polar (1024, 512) code.
To improve the error correction performance of successive cancellation (SC) decoding of polar codes, SC-flip (SCF) decoding was proposed. However, it requires large additional memory to save the decoding history for hardware implementation. This paper proposes a partial sum (PS) memory reduction method and a PS architecture for SCF decoders. We analyze the fractal structure of the generator matrix and propose a logic circuit to decide the corresponding row of the generator matrix for an arbitrary bit-index. The proposed design was implemented on the Xilinx Virtex-7 FPGA, which can reduce the number of flip-flops by up to 47% and the PS history memory size by 94% compared to other PS architectures.
Polar codes are a class of codes discovered recently, which are proved to have capacity-achieving performance. The hardware implementations of successive cancellation (SC) decoding and List SC decoding are increasing dramatically now. However, throughput of these hardware structures remain to be improved on the one hand. On the other hand, stochastic computation is now wildly used because it uses simple structures to implement complicated mathematical operations and thus improves the throughput. This paper extends the application of stochastic computation to the decoding of polar codes. A family of SC decoders based on stochastic computation are proposed, including decoders based on bipolar stochastic computation(BSC-SC), low bits stochastic computation(LBSC-SC) and improved stochastic computation(ISC-SC). These methods have high generality and improve the throughput over SC decoder while having 0.5dB loss in decoding performance. The proposed 32-bit ISC-SC decoder has a better decoding accuracy and improves throughput over BSC-SC. It also reduces the hardware cost and latency compared to LBSC-SC decoder.