International SoC Design Conference

Efficient Partial Sum Architecture and Memory Reduction Method for SC-Flip Polar Decoder

Jae Hong Roh, Useok Lee, Yongje Lee, Myung Hoon Sunwoo

Published Oct 6, 2021• 0 citations

Abstract

To improve the error correction performance of successive cancellation (SC) decoding of polar codes, SC-flip (SCF) decoding was proposed. However, it requires large additional memory to save the decoding history for hardware implementation. This paper proposes a partial sum (PS) memory reduction method and a PS architecture for SCF decoders. We analyze the fractal structure of the generator matrix and propose a logic circuit to decide the corresponding row of the generator matrix for an arbitrary bit-index. The proposed design was implemented on the Xilinx Virtex-7 FPGA, which can reduce the number of flip-flops by up to 47% and the PS history memory size by 94% compared to other PS architectures.

DOI: 10.1109/isocc53507.2021.9613860

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