A method for efficiently successive cancellation (SC) decoding of polar codes with high-dimensional linear binary kernels (HDLBK) is presented and analyzed. We devise a
l-expressions method which can obtain simplified recursive formulas of SC decoder in likelihood ratio form for arbitrary linear binary kernels to reduce the complexity of corresponding SC decoder. By considering the bit-channel transition probabilities
WG(⋅)(⋅∣0) and
WG(⋅)(⋅∣1) separately, a
W-expressions method is proposed to further reduce the complexity of HDLBK based SC decoder. For a
m×m binary kernel, the complexity of straightforward SC decoder is
O(2mNlogN). With
W-expressions, we reduce the complexity of straightforward SC decoder to
O(m2NlogN) when
m≤16. Simulation results show that
16×16 kernel polar codes offer significant advantages in terms of error performances compared with
2×2 kernel polar codes under SC and list SC decoders.
Polar codes are a class of codes discovered recently, which are proved to have capacity-achieving performance. The hardware implementations of successive cancellation (SC) decoding and List SC decoding are increasing dramatically now. However, throughput of these hardware structures remain to be improved on the one hand. On the other hand, stochastic computation is now wildly used because it uses simple structures to implement complicated mathematical operations and thus improves the throughput. This paper extends the application of stochastic computation to the decoding of polar codes. A family of SC decoders based on stochastic computation are proposed, including decoders based on bipolar stochastic computation(BSC-SC), low bits stochastic computation(LBSC-SC) and improved stochastic computation(ISC-SC). These methods have high generality and improve the throughput over SC decoder while having 0.5dB loss in decoding performance. The proposed 32-bit ISC-SC decoder has a better decoding accuracy and improves throughput over BSC-SC. It also reduces the hardware cost and latency compared to LBSC-SC decoder.